After testing and studying the AMD Ryzen™ 7 high-end family of processors, it is time to also take a look at the mainstream Ryzen 5 series, which is offered at very competitive prices and consists of no less than four SKUs:
-Ryzen 5 1400 which does pack four cores and eight threads, with a base speed of 3.2GHz and a boost of 3.4GHz;
-Ryzen 5 1500X that does also come with four physical cores and eight threads, a base speed of 3.5GHz and a boost of 3.7GHz;
-Ryzen 5 1600 which does have no less than six cores, a total of 12 threads; this SKU does come with a base speed of 3.2GHz and a boost of 3.6GHz;
-Ryzen 5 1600X does also pack six cores and 12 threads, but has the highest speeds of the pack: 3.6GHz stock and 4GHz boost.
In this article we will concentrate our attention upon the Ryzen 5 1600X processor, which does have the same operating speeds as the flagship Ryzen 7 1800X model, which means a 3.6GHz stock speed, 3.7GHz all-core boost, 4GHz 2-core boost and also 4.1GHz max boost with XFR. The Ryzen 5 1600X does also have the same 16MB of L3 cache, 512K L2 cache per core, 95W TDP and comes in a 3 + 3 CCX configuration. What does the 3 + 3 CCX configuration you may ask? Well, the Ryzen CPUs are built with CPU Complex (CCX) Zen architecture modules that are natively quad-core and while the Ryzen 7 series had two CCXes available with all CPUs fully-functional, this time with the Ryzen 5 1600X we’ve got also two CCXes but each comes with a disabled core.
Ryzen 5 1600X is integrating the Zen architecture, which focuses on four different key areas: performance, throughput, efficiency but also scalability.
Regarding performance, the new Zen microarchitecture represents a very big leap in core execution capability versus the previous designs from the same company: Zen come with a 1.75X larger instruction scheduler window and 1.5X greater issue width and resources. This practically allows Zen to schedule and send more work into the EUs. Thanks to a new micro-op cache, Zen is allowed to bypass L2 and L3 caches when using frequently accessed micro-operations. The neural network-based branch prediction unit from the Zen microarchitecture does allow for more intelligent preparation of optimal instructions and pathways for future work.
Changes have been also made regarding the cache hierarchy with dedicated 64KB L1 instruction and data caches, we do have 512KB dedicated L2 cache per core and 8MB of L3 cache shared across four cores. The cache is enhanced with a learning prefetcher that speculatively harvests application data into the caches so they are practically available for immediate execution. These changes are assuring up to 5X greater cache bandwidth into a core. This type of design enhances the Zen architecture's throughput.
When talking about efficiency, the new Ryzen processors are built on the more power-efficient 14nm FinFET process; in more detail, the Zen architecture is using the density-optimized version of the Global Foundries 14nm FinFET process and this fact permits for smaller die sizes and lower operating voltages. The new Zen microarchitecture does incorporate some of the latest low-power design technologies:
-micro-op cache for reducing power-intensive faraway fetches
-aggressive clock gating to zero out dynamic power consumption in minimally utilized regions of the core
-a stack engine for low-power address generation into the dispatcher.
Moving on to the scalability aspect, Zen architecture does start with the CCX (CPU Complex) which is a native 4C8T module; each CCX does come with 64K L1 I-cache, 64K L1 D-cache, 512KB of dedicated L2 cache per core and 8MB of L3 cache shared across all cores. Each core that is contained in the CCX may optionally come with SMD for additional threads.
