SOFICS

🎉 Today, we proudly unveil the new Sofics logo. 🎉 More than a mere symbol, it reinforces our evolved identity and underscores our growing prominence. At the forefront of semiconductor design, Sofics specializes in creating Solutions for ICs. The design of our new logo underscores our commitment to excellence in interfaces, PHYs, and I/Os, embodying our dedication to delivering unique and valuable IP solutions. It symbolizes an IC, with a special emphasis on its periphery that highlights our role in safeguarding and enhancing the core of the IC with gold-standard solutions of unparalleled excellence. We elevate IC design by enhancing performance, ensuring superior reliability, and optimizing cost efficiency, thereby empowering designers and IC manufacturers. As we advance, our dedication to innovation and our commitment to customer satisfaction remain unwavering. Join us as we continue to break out of the boundaries of IC design. #Sofics #NewLogoReveal #SolutionsForICs #Innovation #SemiconductorExcellence

🌍 Sofics Continues the Journey at TSMC OIP Forum – Next Stops: Beijing and Amsterdam! 🌍 After a successful presence at TSMC's OIP Forums in Santa Clara and Tokyo, Sofics is excited to join the events in Beijing (November 13) and Amsterdam (November 19)! In Amsterdam we can also take the stage and present about our collaboration with ONiO on their ultra-low power microcontroller, a key solution for the future of battery-less electronics. These TSMC OIP events are a fantastic opportunity to connect with IC designers across regions, discuss the latest in semiconductor advancements, and share our work: unique ESD protection and specialty I/O solutions. Are you also attending the upcoming OIP events? Reach out to schedule a meeting with our team and explore how Sofics can enhance your next IC design. See you soon! 🌐 #Sofics #TSMCOIP #Semiconductor #Innovation #Networking #ChipDesign

🌟 Exploring Careers Beyond Academia: Sofics at the PhD Job Fair 2024 🌟 On Tuesday, November 5, our team members Olivier Marichal and Joren Vaes represented Sofics at the PhD Job Fair 2024 in #Leuven, an inspiring event that bridges academia and industry. This annual fair, organized by PhD Society Leuven, attracted talented PhD students and researchers across disciplines, from engineering to social sciences, all eager to explore impactful industry career paths. Our SOFICS booth saw strong engagement as Olivier and Joren connected with future innovators, discussing how our semiconductor IP solutions are transforming industries worldwide, from smartphones to automotive, IoT, datacenter, AI and beyond. It was a fantastic opportunity to showcase how PhDs can leverage their expertise at Sofics, where innovation thrives and meaningful contributions are made daily. Thank you to everyone who stopped by our booth! We’re excited to stay in touch with talented minds and look forward to seeing where their careers lead. #PhDJobFair2024 #SoficsCareers #SemiconductorInnovation #FutureTalent #PhDOpportunities #BridgingAcademiaAndIndustry

Below some pictures from the Taiwan #ESD and reliability conference last week in Hsinchu. While the second day was spent online due to a strong Typhoon, the first and third day were in-person. Interesting keynotes and invited presentations about 2.5D, 3D integration and most advanced process technologies by YongHoon Yoo, Tzu-Heng Chang, Wen-Chieh Chen. Our colleague Bart Keppens presented about low-cap, small area ESD protection for chiplets' die-2-die interfaces. Let us know if you want a copy of the paper/slide deck.

Currently the annual Taiwan ESD and reliability conference is on-going in Hsinchu. Full program: https://lnkd.in/e8x2dyVH Due to the typhoon Kong-rey reaching Taiwan today, the conference switched to an online mode for the second day. https://lnkd.in/e-iE9i_R Later today, Bart Keppens will present our paper about optimized on-chip ESD protection for high bandwidth chiplet interfaces. Bart will show measurement results from designs on 3nm and 4nm FinFET processes. #chiplet #ESD #lowcap #FinFET

📢 SOFICS is Heading to Beijing! | Join Us at the #TSMC OIP Forum From November 11 to 15, Sofics CEO Koen Verhaege will be in Beijing, engaging with key partners and customers. Jade Ming and the team at Shanghai Lomicro Information Technology Co.,Ltd, our trusted local representation have scheduled several meetings already. 🗓️ On Wednesday, November 13, we are excited to showcase our innovative ESD and custom specialty I/O solutions at the TSMC OIP Forum. You’ll find us at the Hyatt Regency Beijing Wangjing, where we’ll highlight how our silicon-proven IP enables: ✅ Extreme reliability specs (EOS, ESD, EMI, ...) ✅ Lower parasitic capacitance for high-speed interfaces ✅ 100x lower leakage for wireless & sensor applications ✅ Compact, flexible Overvoltage tolerant I/O designs This is a unique opportunity to connect with local IC designers, exchange ideas, and explore how Sofics can help accelerate chip development and enhance performance. 🔗 Let’s meet and discuss your design challenges! Visit us at our booth at the TSMC OIP Forum. Looking forward to seeing you in Beijing! 👋 #Sofics #Semiconductors #TSMCOIP #ESDProtection #IOTechnology #ChipDesign #Fabless #IPSolutions #Beijing

Our colleague Bart Keppens is at the TSMC OIP forum in Japan today. Besides presentations by #TSMC with updates on their technology there are multiple presentation from the OIP ecosystem partners. Also Sofics, a TSMC partner for more than 15 year, was selected for a presentation. Bart talked about the cooperation with ONiO for their ultra-low power MCU product.

🌟 A New Addition to the Sofics Team! 🌟 A few weeks ago we welcomed Andrei Trafimau as our newest employee at SOFICS. Andrei is our new Lab Technician! Andrei plays a crucial role in ensuring our semiconductor IP is validated. He supports many different ESD and circuit analysis techniques like TLP, VF-TLP, HBM, DC, Latch-up, ... Andrei helps us to deliver reliable silicon data for both internal research and customer projects. Currently, Andrei is measuring on 4nm, 5nm, and 14nm FinFET technologies, finalizing reports that will drive future innovation and support our customers' needs. We are excited to have Andrei on board and can’t wait to see the impact of his work in the coming months! 👏 Let’s give him a warm welcome to the team! 🙌 #SoficsTeam #WelcomeToTheTeam #SemiconductorIP #ESDProtection #FinFET #Innovation #Teamwork #SiliconProven

Some highlights from the Topical Workshop on Electronics for Particle Physics (TWEPP 2024 Glasgow) where Wouter Faelens represented SOFICS during the Microelectronics User Group (MUG) meeting. It was an honor to present our innovative ESD protection solutions for thin-oxide transistors in advanced semiconductor processes, alongside experts from around the world. Wouter’s presentation, "Optimizing ESD Protection for Thin-Oxide Transistors in the Latest Semiconductor Processes", sparked insightful discussions on: 🔹 Overcoming traditional ESD protection limitations 🔹 Achieving significant area savings, reduced leakage, and minimized parasitic capacitance 🔹 ESD approaches for radiation-hardened electronics. A big thank you to our contacts at CERN, particularly Kostas Kloukinas, for the invitation and ongoing (more than a decade) partnership, as well as to everyone we connected with. It was a pleasure to exchange ideas and explore future possibilities together! 🔗 Interested in the details? Drop us a message to request the slides from Wouter’s presentation. Check out some of the photos from the event below! 📸 #ESDProtection #Semiconductors #Microelectronics #CERN #RadHard #AdvancedTechnology #Sofics #Innovation #TechCollaboration #ParticlePhysics

🌟 Teamwork Makes the Tape-out Happen! 🌟 Last week, we celebrated a major milestone at SOFICS—our latest test chip tape-out, and as tradition holds, we marked the occasion with a team lunch featuring fries 🍟! But this wasn't just any tape-out—this was our first using the cutting-edge "Gate All Around" (#GAA) technology. Our team has been working tirelessly for months to design and implement new I/O circuits and ESD protection clamps for this advanced node. We can’t wait to see how our innovations will perform when the samples arrive. This milestone represents not only the innovation and expertise of our team but also our commitment to ensuring we have the right IP available and proven before IC designers need it for their new products. 👏 Thank you to the incredible team for the dedication and hard work. #Semiconductors #TestChip #GateAllAround #TeamCelebration #Innovation #ESDProtection #TapeOut #AdvancedTechnology