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ORCIDETS 2004: Ajaccio, France
- 9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004. IEEE Computer Society 2004, ISBN 0-7695-2119-3
- Artur Jutman
:
At-speed on-chip diagnosis of board-level interconnect faults. 2-7 - Octavian Petre, H. G. Kerkho:
Accurate tap-delay measurements using a di .erential oscillation technique. 10-15 - Tian Xia, Peilin Song, Keith A. Jenkins, Jien-Chung Lo:
Delay chain based programmable jitter generator. 16-21 - Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh:
Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits. 24-29 - Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel:
A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder. 30-35 - Bruce R. Parnas, Ankan K. Pramanick, Mark Elston, Toshiaki Adachi:
Software development for an open architecture test system. 38-43 - Ramyanshu Datta, Antony Sebastine, Jacob A. Abraham:
Delay fault testing and silicon debug using scan chains. 46-51 - Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. 52-57 - Norbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet:
Electrically-induced thermal stimuli for MEMS testing. 60-65 - Achraf Dhayni, Salvador Mir, Libor Rufer:
Mems built-in-self-test using MLS. 66-71 - Fei Su, Sule Ozev, Krishnendu Chakrabarty:
Test planning and test resource optimization for droplet-based microfluidic systems. 72-77 - Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre:
User-constrained test architecture design for modular SOC testing. 80-85 - Ozgur Sinanoglu, Alex Orailoglu:
Pipelined test of SOC cores through test data transformations. 86-91 - Kedarnath J. Balakrishnan, Nur A. Touba:
Relating entropy theory to test data compression. 94-99 - Paul Theo Gonciari, Bashir M. Al-Hashimi:
A compression-driven test access mechanism design approach. 100-105 - Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy:
Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. 108-113 - Victor Avendaño, Víctor H. Champac, Joan Figueras:
Signal integrity verification using high speed monitors. 114-119 - Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
Towards a BIST technique for noise figure evaluation. 122-126 - Jee-Youl Ryu, Bruce C. Kim, Iboun Taimiya Sylla:
A new BIST scheme for 5GHz low noise amplifiers. 127-132 - Uros Kac, Franc Novak:
All-pass SC biquad reconfiguration scheme for oscillation based analog BIST. 133-138 - Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. 140-145 - Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars:
Tests for address decoder delay faults in RAMs due to inter-gate opens. 146-151 - Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage? 154-159 - Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Automatic test pattern generation for resistive bridging faults. 160-165 - Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
A design methodology to realize delay testable controllers using state transition information. 168-173 - Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard:
An efficient scan tree design for test time reduction. 174-179
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