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ORCIDACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 1
Volume 1, Number 1, January 1996
- Massoud Pedram:
Power minimization in IC design: principles and applications. 3-56 - Kwang-Ting Cheng
, A. S. Krishnakumar:
Automatic generation of functional vectors using the extended finite state machine model. 57-79 - Yao-Wen Chang, D. F. Wong, C. K. Wong:
Universal switch modules for FPGA design. 80-101 - Shashidhar Thakur, D. F. Wong:
Series-parallel functions and FPGA logic module design. 102-122 - Venkat Thanvantri, Sartaj Sahni:
Optimal folding of standard and custom cells. 123-143
Volume 1, Number 2, April 1996
- Jason Cong, Yuzheng Ding:
Combinational logic synthesis for LUT based field programmable gate arrays. 145-204 - Peter F. A. Middelhoek, Sreeranga P. Rajan:
From VHDL to efficient and first-time-right designs: a formal approach. 205-250 - David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy:
Optimal register assignment to loops for embedded code generation. 251-279 - S. C. Prasad, Kaushik Roy:
Transistor reordering for power minimization under delay constraint. 280-300
Volume 1, Number 3, July 1996
- Wayne H. Wolf:
Object-oriented cosynthesis of distributed embedded systems. 301-314 - Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu:
Low power realization of finite state machines - a decomposition approach. 315-340 - Dimitrios Kagaris, Spyros Tragoudas:
A fast algorithm for minimizing FPGA combinational and sequential modules. 341-351 - En-Shou Chang, Daniel Gajski, Sanjiv Narayan:
An optimal clock period selection method based on slack minimization criteria. 352-370 - Mario Alberto López, Dinesh P. Mehta:
Efficient decomposition of polygons into L-shapes with application to VLSI layouts. 371-395 - R. Moreno, Román Hermida, Milagros Fernández:
Register estimation in unscheduled dataflow graphs. 396-403
Volume 1, Number 4, October 1996
- Kwang-Ting Cheng:
Gate-level test generation for sequential circuits. 405-442 - Michel Langevin, Eduard Cerny:
A recursive technique for computing lower-bound performance of schedules. 443-455 - Rok Sosic, Jun Gu, Robert R. Johnson:
The Unison algorithm: fast evaluation of Boolean expressions. 456-477 - Jason Cong, Lei He:
Optimal wiresizing for interconnects with multiple sources. 478-511 - Joseph L. Ganley, James P. Cohoon:
Rectilinear Steiner trees on a checkerboard. 512-522
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