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2020 – today
- 2024
[c48]Côme Allart
, Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud:
Using a Performance Model to Implement a Superscalar CVA6. CF (Companion) 2024- [c47]Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage:
EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design. IOLTS 2024: 1-7 - [i9]Côme Allart, Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud:
Using a Performance Model to Implement a Superscalar CVA6. CoRR abs/2410.01442 (2024) - 2023
- [j4]Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre:
Experimental EMFI detection on a RISC-V core using the Trace Verifier solution. Microprocess. Microsystems 103: 104968 (2023) - [c46]Raphaël Joud, Pierre-Alain Moëllic, Simon Pontié, Jean-Baptiste Rigaud:
Like an Open Book? Read Neural Network Architecture with Simple Power Analysis on 32-Bit Microcontrollers. CARDIS 2023: 256-276 - [c45]Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre:
A CCFI Verification Scheme Based on the RISC-V Trace Encoder. COSADE 2023: 42-61 - [c44]Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage:
Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations. DATE 2023: 1-2 - [c43]Nathan Roussel, Olivier Potin, Jean-Max Dutertre, Jean-Baptiste Rigaud:
Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation. DATE 2023: 1-6 - [c42]Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage:
A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models. FDTC 2023: 1-12 - [c41]Théophile Gousselot, Olivier Thomas, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud:
Lightweight Countermeasures Against Original Linear Code Extraction Attacks on a RISC-V Core. HOST 2023: 89-99 - [c40]Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre:
CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core. HOST 2023: 100-110 - [i8]Raphaël Joud, Pierre-Alain Moëllic, Simon Pontie, Jean-Baptiste Rigaud:
Like an Open Book? Read Neural Network Architecture with Simple Power Analysis on 32-bit Microcontrollers. CoRR abs/2311.01344 (2023) - 2022
- [c39]Raphaël Joud, Pierre-Alain Moëllic, Simon Pontié, Jean-Baptiste Rigaud:
A Practical Introduction to Side-Channel Extraction of Deep Neural Network Parameters. CARDIS 2022: 45-65 - [c38]Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre:
A CFI Verification System based on the RISC-V Instruction Trace Encoder. DSD 2022: 456-463 - [c37]Nathan Roussel, Olivier Potin, Gregory di Pendina, Jean-Max Dutertre, Jean-Baptiste Rigaud:
CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation. ICECS 2022 2022: 1-4 - [c36]William Souza da Cruz, Raphael Viera, Jean-Baptiste Rigaud, Guillaume Hubert, Jean-Max Dutertre:
An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation. IOLTS 2022: 1-5 - [i7]Raphaël Joud, Pierre-Alain Moëllic, Simon Pontie, Jean-Baptiste Rigaud:
A Practical Introduction to Side-Channel Extraction of Deep Neural Network Parameters. CoRR abs/2211.05590 (2022) - 2021
- [c35]William Souza da Cruz, Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Jean-Baptiste Rigaud, Guillaume Hubert:
Further Analysis of Laser-induced IR-drop. ATS 2021: 91-96 - [c34]Arthur Lavice, Nadia El Mrabet, Alexandre Berzati, Jean-Baptiste Rigaud, Julien Proy:
Hardware Implementations of Pairings at Updated Security Levels. CARDIS 2021: 189-209 - [c33]Arthur Lavice, Nadia El Mrabet, Alexandre Berzati, Jean-Baptiste Rigaud:
Hardware Implementation of Multiplication over Quartic Extension Fields. ICMC 2021: 575-589 - [c32]Raphaël Joud, Pierre-Alain Moëllic, Rémi Bernhard, Jean-Baptiste Rigaud:
A Review of Confidentiality Threats Against Embedded Neural Network Models. WF-IoT 2021: 610-615 - [i6]Raphaël Joud, Pierre-Alain Moëllic, Rémi Bernhard, Jean-Baptiste Rigaud:
A Review of Confidentiality Threats Against Embedded Neural Network Models. CoRR abs/2105.01401 (2021) - 2020
- [c31]Alexandre Menu, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud, Jean-Luc Danger:
Experimental Analysis of the Electromagnetic Instruction Skip Fault Model. DTIS 2020: 1-7 - [c30]Alexandre Menu, Jean-Max Dutertre, Jean-Baptiste Rigaud, Brice Colombier, Pierre-Alain Moëllic, Jean-Luc Danger:
Single-bit Laser Fault Model in NOR Flash Memories: Analysis and Exploitation. FDTC 2020: 41-48 - [c29]William Souza da Cruz, Jean-Max Dutertre, Jean-Baptiste Rigaud, Guillaume Hubert:
Evidence of a Dynamic Fault Model in the DICE Radiation-Hardened Cell. SBCCI 2020: 1-6 - [i5]Arthur Lavice, Nadia El Mrabet, Alexandre Berzati, Jean-Baptiste Rigaud:
Multiplication over Extension Fields for Pairing-based Cryptography: an Hardware Point of View. IACR Cryptol. ePrint Arch. 2020: 1369 (2020)
2010 – 2019
- 2019
- [c28]Alexandre Menu, Shivam Bhasin, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger:
Precise Spatio-Temporal Electromagnetic Fault Injections on Data Transfers. FDTC 2019: 1-8 - [c27]Brice Colombier, Alexandre Menu, Jean-Max Dutertre, Pierre-Alain Moëllic, Jean-Baptiste Rigaud, Jean-Luc Danger:
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller. HOST 2019: 1-10 - [c26]Jean-Max Dutertre, Timothée Riom, Olivier Potin, Jean-Baptiste Rigaud:
Experimental Analysis of the Laser-Induced Instruction Skip Fault Model. NordSec 2019: 221-237 - 2018
- [i4]Brice Colombier, Alexandre Menu, Jean-Max Dutertre, Pierre-Alain Moëllic, Jean-Baptiste Rigaud, Jean-Luc Danger:
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller. IACR Cryptol. ePrint Arch. 2018: 1042 (2018) - 2017
- [j3]Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout:
A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs. J. Hardw. Syst. Secur. 1(3): 219-236 (2017) - 2016
- [c25]Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout:
High-Performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication. CRiSIS 2016: 185-198 - [c24]David El-Baze, Jean-Baptiste Rigaud, Philippe Maurine:
A fully-digital EM pulse detector. DATE 2016: 439-444 - [c23]Marc Lacruche, Noemie Beringuier-Boher, Jean-Max Dutertre, Jean-Baptiste Rigaud, Edith Kussener:
On the use of Forward Body Biasing to decrease the repeatability of laser-induced faults. DATE 2016: 547-550 - [c22]David El-Baze, Jean-Baptiste Rigaud, Philippe Maurine:
An Embedded Digital Sensor against EM and BB Fault Injection. FDTC 2016: 78-86 - [c21]Noemie Beringuier-Boher, Marc Lacruche, David El-Baze, Jean-Max Dutertre, Jean-Baptiste Rigaud, Philippe Maurine:
Body Biasing Injection Attacks in Practice. CS2@HiPEAC 2016: 49-54 - [c20]Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout:
A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs. SPACE 2016: 138-156 - [i3]Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout:
A Systolic Hardware Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems. IACR Cryptol. ePrint Arch. 2016: 487 (2016) - 2015
- [c19]Xuan Thuy Ngo, Ingrid Exurville, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm, Jean-Baptiste Rigaud, Bruno Robisson:
Hardware trojan detection by delay and electromagnetic measurements. DATE 2015: 782-787 - [c18]Loïc Zussa, Ingrid Exurville, Jean-Max Dutertre, Jean-Baptiste Rigaud, Bruno Robisson, Assia Tria, Jessy Clédière:
Evidence of an information leakage between logically independent blocks. CS2@HiPEAC 2015: 25-30 - [c17]Ingrid Exurville, Loïc Zussa, Jean-Baptiste Rigaud, Bruno Robisson:
Resilient hardware Trojans detection based on path delay measurements. HOST 2015: 151-156 - [c16]Marc Lacruche, Nicolas Borrel, Clement Champeix, Cyril Roscian, Alexandre Sarafianos, Jean-Baptiste Rigaud, Jean-Max Dutertre, Edith Kussener:
Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses. IOLTS 2015: 13-18 - 2014
- [c15]Noemie Beringuier-Boher, Kamil Gomina, David Hély, Jean-Baptiste Rigaud, Vincent Beroulle, Assia Tria, Joel Damiens, Philippe Gendrier, Philippe Candelier:
Voltage Glitch Attacks on Mixed-Signal Systems. DSD 2014: 379-386 - [c14]Kamil Gomina, Philippe Gendrier, Philippe Candelier, Jean-Baptiste Rigaud, Assia Tria:
Detecting positive voltage attacks on CMOS circuits. CS2@HiPEAC 2014: 1-6 - [c13]Kamil Gomina, Jean-Baptiste Rigaud, Philippe Gendrier, Philippe Candelier, Assia Tria:
Power supply glitch attacks: Design and evaluation of detection circuits. HOST 2014: 136-141 - [i2]Sébastien Tiran, Guillaume Reymond, Jean-Baptiste Rigaud, Driss Aboulkassimi, Benedikt Gierlichs, Mathieu Carbone, Gilles R. Ducharme, Philippe Maurine:
Analysis Of Variance and CPA in SCA. IACR Cryptol. ePrint Arch. 2014: 707 (2014) - 2013
- [c12]Kamil Gomina, Jean-Baptiste Rigaud, Philippe Gendrier, Philippe Candelier, Assia Tria:
Power analysis methodology for secure circuits. DDECS 2013: 102-107 - 2011
- [j2]Jacques J. A. Fournier, Jean-Baptiste Rigaud, Sylvain Bouquet, Bruno Robisson, Assia Tria, Jean-Max Dutertre, Michel Agoyan:
Design and characterisation of an AES chip embedding countermeasures. Int. J. Intell. Eng. Informatics 1(3/4): 328-347 (2011) - [c11]Marion Doulcier-Verdier, Jean-Max Dutertre, Jacques J. A. Fournier, Jean-Baptiste Rigaud, Bruno Robisson, Assia Tria:
A side-channel and fault-attack resistant AES circuit working on duplicated complemented values. ISSCC 2011: 274-276 - 2010
- [c10]Jean-Baptiste Rigaud, Jean-Max Dutertre, Michel Agoyan, Bruno Robisson, Assia Tria:
Experimental Fault Injection based on the Prototyping of an AES Cryptosystem. ReCoSoC 2010: 141-147
2000 – 2009
- 2008
- [c9]Julien Francq, Jean-Baptiste Rigaud, Pascal Manet, Assia Tria, Arnaud Tisserand:
Error Detection for Borrow-Save Adders Dedicated to ECC Unit. FDTC 2008: 77-86 - 2007
- [j1]Marc Joye, Pascal Manet, Jean-Baptiste Rigaud:
Strengthening hardware AES implementations against fault attacks. IET Inf. Secur. 1(3): 106-110 (2007) - [c8]Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria:
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. DATE 2007: 1587-1592 - [i1]Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud:
Hardware Engines for Bus Encryption: A Survey of Existing Techniques. CoRR abs/0710.4803 (2007) - 2006
- [c7]Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Assia Tria, Bruno Robisson, Jerome Quartana, Selma Laabidi:
Integrated Evaluation Platform for Secured Devices. ReCoSoC 2006: 214-219 - 2005
- [c6]Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud:
Hardware Engines for Bus Encryption: A Survey of Existing Techniques. DATE 2005: 40-45 - 2003
- [c5]Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani:
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279 - [c4]Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin:
Statistic Implementation of QDI Asynchronous Primitives. PATMOS 2003: 181-191 - 2002
- [b1]Jean-Baptiste Rigaud:
Spécification de bibliothèques pour la synthèse de circuits asynchrones. (Libraries specification for the synthesis of asynchronous circuits). Grenoble Institute of Technology, France, 2002 - [c3]Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana:
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090 - [c2]Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland:
Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46 - 2001
- [c1]Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324
Coauthor Index
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