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ORCIDGiacomo Valente
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- affiliation: University of L'Aquila, Italy
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2020 – today
- 2024
[j6]Giacomo Valente
, Vittoriano Muttillo, Fabio Federici, Luigi Pomante, Tania Di Mascio:
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection. IEEE Embed. Syst. Lett. 16(2): 162-165 (2024)- [c27]Gianluca Brilli, Giacomo Valente, Alessandro Capotondi, Tania Di Mascio, Andrea Marongiu:
Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip. WCET 2024: 5:1-5:11 - 2023
- [j5]Vittoriano Muttillo, Luigi Pomante, Marco Santic, Giacomo Valente:
SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design. Comput. Electr. Eng. 110: 108803 (2023) - [c26]Gianluca Brilli, Giacomo Valente, Alessandro Capotondi, Paolo Burgio, T. Di Masciov, Paolo Valente, Andrea Marongiu:
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs. DAC 2023: 1-6 - 2022
- [c25]Federica Caruso, Tania Di Mascio, Daniele Frigioni, Luigi Pomante, Giacomo Valente, Stefano Delucchi, Paolo Burgio, Manuel Di Frangia, Luca Paganin, Chiara Garibotto, Damiano Vallocchia:
Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project. DSD 2022: 741-747 - 2021
- [j4]Giacomo Valente, Tania Di Mascio, Luigi Pomante, Gabriella D'Andrea:
Dynamic Partial Reconfiguration Profitability for Real-Time Systems. IEEE Embed. Syst. Lett. 13(3): 102-105 (2021) - [j3]Carlo Sau, Claudia Rinaldi, Luigi Pomante, Francesca Palumbo, Giacomo Valente, Tiziana Fanni, Marcos Martinez de Alejandro, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jirí Kadlec, Pekka Jääskeläinen, Lubomír Bulej, Francisco Barranco, Jukka Saarinen, Tero Säntti, Maria Katiuscia Zedda, Victor Sanchez, Shayan Tabatabaei Nikkhah, Dip Goswami, Guillermo Amat, Lukás Marsík, Mark van Helvoort, Luis Medina, Zaid Al-Ars, Ad de Beer:
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project. Microprocess. Microsystems 87: 104350 (2021) - [j2]Giacomo Valente, Tiziana Fanni, Carlo Sau, Tania Di Mascio, Luigi Pomante, Francesca Palumbo:
A Composable Monitoring System for Heterogeneous Embedded Platforms. ACM Trans. Embed. Comput. Syst. 20(5): 42:1-42:34 (2021) - [c24]Tania Di Mascio, Federica Caruso, Laura Tarantino, Giacomo Valente:
MONICA Vision: An Approach, a Model and the Interactive Tools for Cyber-Physical Systems Designers. CHItaly 2021: 33:1-33:5 - [c23]Gabriella D'Andrea, Giacomo Valente, Luigi Pomante, Tania Di Mascio:
An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems. DSD 2021: 192-198 - [c22]Federica Caruso, Tania Di Mascio, Sara Peretti, Luigi Pomante, Giacomo Valente:
MONICA "On-the-Job" Technology-Enhanced Learning Environment: An Empirical Evaluation. MIS4TEL 2021: 54-64 - [i1]Giacomo Valente, Tiziana Fanni, Carlo Sau, Francesco Di Battista:
Layering the monitoring action for improved flexibility and overhead control: work-in-progress. CoRR abs/2103.01176 (2021) - 2020
- [c21]Giacomo Valente, Tiziana Fanni, Carlo Sau, Francesco Di Battista:
Layering the monitoring action for improved flexibility and overhead control: work-in-progress. CODES+ISSS 2020: 18-20 - [c20]Giacomo Valente, Tania Di Mascio, Luigi Pomante, Vincenzo Stoico:
An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the "Design for Monitorability" Project - Work-in-Progress. CODES+ISSS 2020: 40-42 - [c19]Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Hector Posadas, Javier Merino, Eugenio Villar:
Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow. DSD 2020: 117-125 - [c18]Luigi Pomante, Francesca Palumbo, Claudia Rinaldi, Giacomo Valente, Carlo Sau, Tiziana Fanni, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jirí Kadlec, Pekka Jääskeläinen, Marcos Martinez de Alejandro, Jukka Saarinen, Tero Säntti, Maria Katiuscia Zedda, Victor Sanchez, Dip Goswami, Zaid Al-Ars, Ad de Beer:
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project. DSD 2020: 378-385 - [c17]Gabriella D'Andrea, Giacomo Valente:
Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges. RTSS 2020: 399-402
2010 – 2019
- 2019
- [c16]Paolo Giammatteo, Giacomo Valente, Alessandro D'Ortenzio:
An Intelligent Informative Totem Application Based on Deep CNN in Edge Regime. ApplePies 2019: 191-198 - [c15]Gabriella D'Andrea, Tania Di Mascio, Giacomo Valente:
Self-adaptive loop for CPSs: is the Dynamic Partial Reconfiguration profitable? MECO 2019: 1-5 - 2018
- [c14]Vittoriano Muttillo, Giacomo Valente, Luigi Pomante:
Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions. DSD 2018: 740-744 - [c13]Vittoriano Muttillo, Giacomo Valente, Luigi Pomante:
Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems. PARMA-DITAM@HiPEAC 2018: 63-68 - [c12]Daniele Ciambrone, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente:
HEPSIM: An ESL HW/SW co-simulator/analysis tool for heterogeneous parallel embedded systems. MECO 2018: 1-6 - [c11]Vittoriano Muttillo, Giacomo Valente:
Injecting hypervisor-based software partitions into Design Space Exploration activities considering mixed-criticality requirements. MECO 2018: 1-5 - [c10]Vittoriano Muttillo, Giacomo Valente, Daniele Ciambrone, Vincenzo Stoico, Luigi Pomante:
HEPSYCODE-RT: a Real-Time Extension for an ESL HW/SW Co-Design Methodology. RAPIDO 2018: 6:1-6:6 - [c9]Vittoriano Muttillo, Giacomo Valente, Luigi Pomante:
Criticality-aware Design Space Exploration for Mixed-Criticality Embedded Systems. ICPE Companion 2018: 45-46 - [c8]Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Vincenzo Stoico, Fausto D'Antonio, Fabio Salice:
CC4CS: an Off-the-Shelf Unifying Statement-Level Performance Metric for HW/SW Technologies. ICPE Companion 2018: 119-122 - 2017
- [b1]Giacomo Valente:
A HW/SW unified approach for embedded systems monitoring. University of L'Aquila, Italy, 2017 - [c7]Fabio Federici, Mattia Micozzi, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente:
Simulation-Based Analysis of a Hardware Mechanism to Support Isolation in Mixed-Criticality Network on Chip. EMS 2017: 185-190 - [c6]Giacomo Valente, Marco Rotondi, Vittoriano Muttillo:
Time Bands: A Software Approach for Timing Analysis on Resource Constrained Systems. ICPE 2017: 161-162 - [c5]Daniele Di Pompeo, Emilio Incerto, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente:
An Efficient Performance-Driven Approach for HW/SW Co-Design. ICPE 2017: 323-326 - 2016
- [j1]Vittoriano Muttillo, Giacomo Valente, Fabio Federici, Luigi Pomante, Marco Faccio, Carlo Tieri, Serenella Ferri:
A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system. EURASIP J. Embed. Syst. 2016: 15 (2016) - [c4]Giacomo Valente, Vittoriano Muttillo, Luigi Pomante, Fabio Federici, Marco Faccio, Andrea Moro, Serenella Ferri, Carlo Tieri:
A Flexible Profiling Sub-System for Reconfigurable Logic Architectures. PDP 2016: 373-376 - [c3]Marco Faccio, Fabio Federici, Giuseppe Marini, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente:
Design and validation of multi-core embedded systems under time-to-prototype and high performance constraints. RTSI 2016: 1 - 2015
- [c2]Giacomo Valente:
A framework for integrated monitoring of real-time embedded SoC. FPL 2015: 1-2 - [c1]Andrea Moro, Fabio Federici, Giacomo Valente, Luigi Pomante, Marco Faccio, Vittoriano Muttillo:
Hardware performance sniffers for embedded systems profiling. WISES 2015: 29-34
Coauthor Index
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last updated on 2024-10-07 21:24 CEST by the dblp team
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