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ORCIDYoung-Hwa Kim
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2020 – today
- 2020
[j4]Kyung-Soo Ha
, Seungseob Lee, Youn-Sik Park, Hyuck-Joon Kwon, Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Young-Hwa Kim, Young Hoon Son, Byongwook Na:
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. IEEE J. Solid State Circuits 55(1): 157-166 (2020)
2010 – 2019
- 2019
- [c4]Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, Seungseob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. ISSCC 2019: 378-380 - 2016
- [j3]Young-Hwa Kim, SeongHwan Cho:
A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2570-2579 (2016) - 2015
- [j2]Jungho Kim, Young-Hwa Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho:
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 631-635 (2015) - 2013
- [j1]KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho:
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. IEEE J. Solid State Circuits 48(4): 1009-1017 (2013) - 2012
- [c3]KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho:
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. VLSIC 2012: 192-193 - 2011
- [c2]Young-Hwa Kim, SeongHwan Cho:
A time-domain flash ADC immune to voltage controlled delay line non-linearity. ASICON 2011: 469-471 - 2010
- [c1]Young-Hwa Kim, Jaewon Lee, SeongHwan Cho:
A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. ISCAS 2010: 4041-4044
Coauthor Index
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