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2020 – today
- 2023
[j82]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 542-550 (2023)- 2022
- [j81]Yih-Lang Li
, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5568-5581 (2022) - [c138]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region. LASCAS 2022: 1-4 - [c137]Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera:
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC 2022: 1-6 - 2021
- [j80]Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1488-1498 (2021) - [j79]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1546-1554 (2021) - [j78]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1566-1576 (2021) - [j77]Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera:
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation. IEICE Trans. Electron. 104-C(10): 617-624 (2021) - [j76]Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera:
Supplemental PDK for ASAP7 Using Synopsys Flow. IPSJ Trans. Syst. LSI Des. Methodol. 14: 24-26 (2021) - [j75]Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching. IEEE Open J. Circuits Syst. 2: 144-155 (2021) - [c136]Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. DAC 2021: 139-144 - [c135]Kensuke Murakami, Mahfuzul Islam, Hidetoshi Onodera:
CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models. IOLTS 2021: 1-6 - 2020
- [j74]Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. IEICE Trans. Electron. 103-C(10): 489-496 (2020) - [c134]Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera:
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias. APCCAS 2020: 31-34 - [c133]Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation. ACM Great Lakes Symposium on VLSI 2020: 21-26 - [c132]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera:
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. ICCAD 2020: 157:1-157:8 - [c131]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. ICRC 2020: 95-101 - [c130]Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi:
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504 - [c129]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. ISVLSI 2020: 488-493 - [c128]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region. SoCC 2020: 236-241
2010 – 2019
- 2019
- [j73]Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A Design Method of a Cell-Based Amplifier for Body Bias Generation. IEICE Trans. Electron. 102-C(7): 565-572 (2019) - [j72]Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera:
Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. IEICE Trans. Electron. 102-C(7): 573-579 (2019) - [j71]Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1741-1750 (2019) - [j70]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1751-1759 (2019) - [j69]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. Integr. 65: 201-210 (2019) - [j68]A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation. IPSJ Trans. Syst. LSI Des. Methodol. 12: 2-12 (2019) - [c127]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. ASP-DAC 2019: 203-209 - [c126]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. DAC 2019: 120 - [c125]A. K. M. Mahfuzul Islam, Ryota Shimizu, Hidetoshi Onodera:
Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators. IRPS 2019: 1-6 - [c124]Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. SoCC 2019: 150-154 - 2018
- [j67]Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto:
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10(4): 119-122 (2018) - [j66]Shinichi Nishizawa, Hidetoshi Onodera:
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2222-2230 (2018) - [j65]Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
Minimum Energy Point Tracking with All-Digital On-Chip Sensors. J. Low Power Electron. 14(2): 227-235 (2018) - [j64]Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto:
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - [c123]Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. A-SSCC 2018: 69-72 - [c122]A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
PVT2: process, voltage, temperature and time-dependent variability in scaled CMOS process. ICCAD 2018: 126 - [c121]Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi:
Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics. ICRC 2018: 1-8 - [c120]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. ICRC 2018: 1-6 - [c119]Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera:
Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. IOLTS 2018: 177-182 - [c118]Shinichi Nishizawa, Hidetoshi Onodera:
Process variation aware D-Flip-Flop design using regression analysis. ISQED 2018: 88-93 - [c117]Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology. MWSCAS 2018: 751-754 - [c116]A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability. PATMOS 2018: 140-146 - [c115]Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. PATMOS 2018: 237-242 - [c114]Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera:
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. SoCC 2018: 112-117 - 2017
- [j63]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2764-2775 (2017) - [j62]Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2776-2784 (2017) - [c113]Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera:
Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication. MWSCAS 2017: 795-798 - [c112]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
Effect of supply voltage on random telegraph noise of transistors under switching condition. PATMOS 2017: 1-8 - [c111]Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera:
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC 2017: 56-61 - [c110]Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera:
On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator. VLSI-DAT 2017: 1-4 - 2016
- [j61]Hidetoshi Onodera:
2016 ASP-DAC. IEEE Des. Test 33(3): 133-134 (2016) - [j60]Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2463-2472 (2016) - [c109]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations. ASP-DAC 2016: 403-409 - [c108]Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. ASP-DAC 2016: 691-696 - [c107]Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto:
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4 - [c106]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Variability- and correlation-aware logical effort for near-threshold circuit design. ISQED 2016: 18-23 - [c105]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. PATMOS 2016: 44-49 - [c104]Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing. SoCC 2016: 1-6 - 2015
- [j59]Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera:
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets. IEICE Trans. Electron. 98-C(4): 298-303 (2015) - [j58]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage. IEICE Trans. Electron. 98-C(6): 504-511 (2015) - [j57]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1455-1466 (2015) - [j56]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. IPSJ Trans. Syst. LSI Des. Methodol. 8: 131-135 (2015) - [j55]Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. IEEE J. Solid State Circuits 50(11): 2475-2490 (2015) - [j54]Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera:
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1288-1295 (2015) - [c103]Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera:
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - [c102]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Microarchitectural-level statistical timing models for near-threshold circuit design. ASP-DAC 2015: 87-93 - [c101]Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura:
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. A-SSCC 2015: 1-4 - [c100]Chenjie Gu, Hidetoshi Onodera:
Session 23 - Modeling emerging devices. CICC 2015: 1 - [c99]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
An energy-efficient on-chip memory structure for variability-aware near-threshold operation. ISQED 2015: 23-28 - [c98]Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera:
Energy reduction by built-in body biasing with single supply voltage operation. ISQED 2015: 181-185 - [c97]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
An impact of process variation on supply voltage dependence of logic path delay variation. VLSI-DAT 2015: 1-4 - 2014
- [j53]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 734-740 (2014) - [j52]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 768-776 (2014) - [j51]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure. IEICE Trans. Electron. 97-C(4): 325-331 (2014) - [j50]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera:
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014) - [j49]Bishnu Prasad Das, Hidetoshi Onodera:
On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 183-187 (2014) - [j48]Bishnu Prasad Das, Hidetoshi Onodera:
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2535-2548 (2014) - [c96]Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. A-SSCC 2014: 45-48 - [c95]Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera:
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation. A-SSCC 2014: 53-56 - [c94]Yukio Mitsuyama, Hidetoshi Onodera:
Variability and Soft-Error Resilience in Dependable VLSI Platform. ATS 2014: 45-50 - [c93]Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
Impact of random telegraph noise on CMOS logic circuit reliability. CICC 2014: 1-8 - [c92]Colin McAndrew, Hidetoshi Onodera:
Modeling of advanced devices. CICC 2014: 1 - [c91]Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai:
A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. ISCAS 2014: 2704-2707 - [c90]Tomohiro Fujita, SinNyoung Kim, Hidetoshi Onodera:
Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model. ISQED 2014: 230-235 - [c89]Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Variation-aware Flip-Flop energy optimization for ultra low voltage operation. SoCC 2014: 17-22 - [c88]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. SoCC 2014: 42-47 - [c87]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
Characterization and compensation of performance variability using on-chip monitors. VLSI-DAT 2014: 1-4 - 2013
- [j47]Kuiyuan Zhang, Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect. IEICE Trans. Electron. 96-C(4): 511-517 (2013) - [j46]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation. IEICE Trans. Inf. Syst. 96-D(9): 1971-1979 (2013) - [j45]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2499-2507 (2013) - [c86]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. ASP-DAC 2013: 105-106 - [c85]Hidetoshi Onodera:
Dependable VLSI Platform using Robust Fabrics. ASP-DAC 2013: 119-124 - [c84]Hidetoshi Onodera, Yu Kevin Cao:
AMS verification in advanced technologies. CICC 2013: 1 - [c83]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Perturbation-immune radiation-hardened PLL with a switchable DMR structure. IOLTS 2013: 128-132 - [c82]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Analysis and comparison of XOR cell structures for low voltage circuit design. ISQED 2013: 703-708 - 2012
- [j44]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 479-486 (2012) - [j43]Bishnu Prasad Das, Hidetoshi Onodera:
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation. IET Circuits Devices Syst. 6(6): 429-436 (2012) - [c81]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. ASP-DAC 2012: 561-562 - [c80]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation. Asian Test Symposium 2012: 350-354 - [c79]Trent McConaghy, Hidetoshi Onodera:
Modeling & design for variability and reliability. CICC 2012: 1-2 - [c78]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A flexible structure of standard cell and its optimization method for near-threshold voltage operation. ICCD 2012: 235-240 - [c77]Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A Standard Cell Optimization Method for Near-Threshold Voltage Operations. PATMOS 2012: 32-41 - 2011
- [j42]Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera:
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2669-2675 (2011) - [j41]Hidetoshi Onodera:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 4: 1 (2011) - [c76]Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. ASP-DAC 2011: 83-84 - [c75]Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. A-SSCC 2011: 209-212 - [c74]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
An area effective forward/reverse body bias generator for within-die variability compensation. A-SSCC 2011: 217-220 - [c73]Hidetoshi Onodera:
Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project. Asian Test Symposium 2011: 492-495 - [c72]Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera:
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. ISOCC 2011: 36-39 - [c71]Shigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS. ISOCC 2011: 223-226 - [c70]Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera:
Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation. ISQED 2011: 22-27 - 2010
- [j40]Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera:
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity. IEICE Trans. Electron. 93-C(3): 340-346 (2010) - [j39]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. Inf. Media Technol. 5(2): 424-433 (2010) - [j38]Hidetoshi Onodera:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 3: 1 (2010) - [j37]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. IPSJ Trans. Syst. LSI Des. Methodol. 3: 130-139 (2010) - [c69]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. CICC 2010: 1-4 - [c68]Bishnu Prasad Das, Hidetoshi Onodera:
Warning Prediction Sequential for Transient Error Prevention. DFT 2010: 382-390 - [c67]Hiroki Sunagawa, Hidetoshi Onodera:
Variation-tolerant design of D-flipflops. SoCC 2010: 147-151 - [c66]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
A design procedure of predictive RF MOSFET model for compatibility with ITRS. SoCC 2010: 396-399
2000 – 2009
- 2009
- [j36]Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Statistical Gate Delay Model for Multiple Input Switching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3070-3078 (2009) - [j35]Hidetoshi Onodera:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 2: 1 (2009) - [c65]Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe:
Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC 2009: 859-860 - [c64]Gennady Gildenblat, Hidetoshi Onodera:
Modeling of passive elements and reliability. CICC 2009 - [c63]Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Erect of regularity-enhanced layout on printability and circuit performance of standard cells. ISQED 2009: 195-200 - 2008
- [j34]Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera:
Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Trans. Inf. Syst. 91-D(3): 655-660 (2008) - [j33]Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera:
Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration. IEICE Trans. Electron. 91-C(9): 1488-1500 (2008) - [j32]Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. Inf. Media Technol. 3(4): 729-738 (2008) - [j31]Hidetoshi Onodera:
Welcome to TSLDM - A New Open-Access Online Journal from IPSJ. IPSJ Trans. Syst. LSI Des. Methodol. 1: 1 (2008) - [j30]Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. IPSJ Trans. Syst. LSI Des. Methodol. 1: 116-125 (2008) - [c62]Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Statistical gate delay model for Multiple Input Switching. ASP-DAC 2008: 286-291 - [c61]Kazutoshi Kobayashi, Hidetoshi Onodera:
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. ASP-DAC 2008: 811-812 - [c60]Hidetoshi Onodera, Hong-Ha Vuong:
Session 2 - Statistical modeling. CICC 2008 - [c59]Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera:
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. FPGA 2008: 257 - [c58]Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera:
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. FPL 2008: 107-112 - [c57]Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera:
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. FPL 2008: 503-506 - 2007
- [j29]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations. IEICE Trans. Electron. 90-C(4): 699-707 (2007) - [j28]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Trans. Electron. 90-C(6): 1267-1273 (2007) - [j27]Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera:
Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver. IEICE Trans. Electron. 90-C(6): 1274-1281 (2007) - [j26]Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera:
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations. IEICE Trans. Electron. 90-C(10): 1919-1926 (2007) - [j25]Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera:
Timing Analysis Considering Spatial Power/Ground Level Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2661-2668 (2007) - [j24]Hirokazu Muta, Hidetoshi Onodera:
Manufacturability-Aware Design of Standard Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2682-2690 (2007) - [c56]Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera:
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. ASP-DAC 2007: 120-121 - [c55]Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. ASP-DAC 2007: 122-123 - [c54]Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Worst-case delay analysis considering the variability of transistors and interconnects. ISPD 2007: 35-42 - 2006
- [j23]Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. IEICE Trans. Electron. 89-C(3): 327-333 (2006) - [j22]Hidetoshi Onodera:
Variability: Modeling and Its Impact on Design. IEICE Trans. Electron. 89-C(3): 342-348 (2006) - [j21]Kazutoshi Kobayashi, Akihiko Higuchi, Hidetoshi Onodera:
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era. IEICE Trans. Electron. 89-C(6): 838-843 (2006) - [j20]Hidetoshi Onodera:
Special Section on VLSI Design and CAD Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3377 (2006) - [j19]Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto:
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3560-3568 (2006) - [j18]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3585-3593 (2006) - [c53]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. ASP-DAC 2006: 110-111 - [c52]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Interconnect RL extraction at a single representative frequency. ASP-DAC 2006: 515-520 - [c51]Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera:
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. FPL 2006: 1-4 - [c50]Takeshi Kouno, Hidetoshi Onodera:
Consideration of Transition-Time Variability in Statistical Timing Analysis. SoCC 2006: 207-210 - [c49]Masanao Yamaoka, Hidetoshi Onodera:
A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. SoCC 2006: 315-318 - 2005
- [j17]Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera:
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL. IEICE Trans. Electron. 88-C(3): 437-444 (2005) - [j16]Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera:
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era. IEICE Trans. Electron. 88-C(4): 552-558 (2005) - [j15]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 885-891 (2005) - [j14]Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera:
Statistical Analysis of Clock Skew Variation in H-Tree Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3375-3381 (2005) - [j13]Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera:
Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3429-3436 (2005) - [j12]Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera:
Effects of On-Chip Inductance on Power Distribution Grid. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3564-3572 (2005) - [c48]Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera:
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. ASP-DAC 2005: 9-10 - [c47]Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera:
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. ASP-DAC 2005: 619-622 - [c46]Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera:
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC 2005: 723-728 - [c45]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Return path selection for loop RL extraction. ASP-DAC 2005: 1078-1081 - [c44]Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera:
Timing analysis considering temporal supply voltage fluctuation. ASP-DAC 2005: 1098-1101 - [c43]Steffen Rochel, Hidetoshi Onodera:
Substrate and phase noise characterization. CICC 2005: 448-449 - [c42]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
A yield and speed enhancement scheme under within-die variations on 90nm LUT array. CICC 2005: 601-604 - [c41]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Design guideline for resistive termination of on-chip high-speed interconnects. CICC 2005: 613-616 - [c40]Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera:
Effects of on-chip inductance on power distribution grid. ISPD 2005: 63-69 - [c39]Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera:
Statistical Analysis of Clock Skew Variation in H-Tree Structure. ISQED 2005: 402-407 - 2004
- [j11]Kazutoshi Kobayashi, Hidetoshi Onodera:
A Comprehensive Simulation and Test Environment for Prototype VLSI Verification. IEICE Trans. Inf. Syst. 87-D(3): 630-636 (2004) - [j10]Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera:
Equivalent waveform propagation for static timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 498-508 (2004) - [c38]Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera:
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. ASP-DAC 2004: 545-546 - [c37]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC 2004: 691-696 - [c36]Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
An SoC architecture and its design methodology using unifunctional heterogeneous processor array. ASP-DAC 2004: 737-742 - [c35]Akira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera:
Performance limitation of on-chip global interconnects for high-speed signaling. CICC 2004: 489-492 - [c34]Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera:
Timing analysis considering spatial power/ground level variation. ICCAD 2004: 814-820 - [c33]Ken-ichi Okada, Hiroaki Hoshino, Hidetoshi Onodera:
Modelling and optimization of on-chip spiral inductor in S-parameter domain. ISCAS (5) 2004: 153-156 - [c32]Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
RTL/ISS co-modeling methodology for embedded processor using SystemC. ISCAS (5) 2004: 305-308 - [c31]Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera:
Automatic Generation of Standard Cell Library in VDSM Technologies. ISQED 2004: 36-41 - 2003
- [j9]Kenichi Okada, Hidetoshi Onodera:
Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4): 746-751 (2003) - [j8]Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera:
Statistical Gate-Delay Modeling with Intra-Gate Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2914-2922 (2003) - [j7]Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera:
Representative Frequency for Interconnect R(f)L(f)C Extraction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2942-2951 (2003) - [j6]Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera:
Crosstalk Noise Estimation for Generic RC Trees. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2965-2973 (2003) - [j5]Masanori Hashimoto, Yoshiteru Hayashi, Hidetoshi Onodera:
Experimental Study on Cell-Base High-Performance Datapath Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3204-3207 (2003) - [c30]Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera:
A statistical gate delay model for intra-chip and inter-chip variabilities. ASP-DAC 2003: 31-36 - [c29]Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera:
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies. ASP-DAC 2003: 589-590 - [c28]Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera:
Equivalent Waveform Propagation for Static Timing Analysis. ICCAD 2003: 169-175 - [c27]Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera:
A Statistical Gate-Delay Model Considering Intra-Gate Variability. ICCAD 2003: 908-913 - [c26]Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera:
Statistical modeling of gate-delay variation with consideration of intra-gate variability. ISCAS (5) 2003: 513-516 - [c25]Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera:
Capturing crosstalk-induced waveform for accurate static timing analysis. ISPD 2003: 18-23 - 2002
- [j4]Masanori Hashimoto, Hidetoshi Onodera:
Increase in Delay Uncertainty by Performance Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2799-2802 (2002) - [c24]Kazutoshi Kobayashi, Junji Yamaguchi, Hidetoshi Onodera:
Measurement results of on-chip IR-drop. CICC 2002: 521-524 - [c23]Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera:
Crosstalk noise optimization by post-layout transistor sizing. ISPD 2002: 126-130 - [c22]Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera:
Experimental Study on Cell-Base High-Performance Datapath Design. IWLS 2002: 283-287 - 2001
- [c21]Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera:
A vector-pipeline DSP for low-rate videophones. ASP-DAC 2001: 1-2 - [c20]Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori:
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. ASP-DAC 2001: 267-268 - [c19]Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera:
A dynamically phase adjusting PLL with a variable delay. ASP-DAC 2001: 275-280 - [c18]Masanori Hashimoto, Hidetoshi Onodera:
Post-layout transistor sizing for power reduction in cell-based design. ASP-DAC 2001: 359-365 - [c17]Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera:
Crosstalk Noise Estimation for Generic RC Trees. ICCD 2001: 110-117 - [c16]Kazutoshi Kobayashi, Hidetoshi Onodera:
ST: PERL package for simulation and test environment. ISCAS (5) 2001: 89-92 - 2000
- [c15]Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru:
A method for linking process-level variability to system performances. ASP-DAC 2000: 547-552 - [c14]Kenichi Okada, Hidetoshi Onodera:
Statistical modeling of device characteristics with systematic fluctuation. ISCAS 2000: 437-440 - [c13]Tomohiro Fujita, Hidetoshi Onodera:
Statistical delay calculation with vector synthesis model. ISCAS 2000: 473-476 - [c12]Masanori Hashimoto, Hidetoshi Onodera:
A performance optimization method by gate sizing using statistical static timing analysis. ISPD 2000: 111-116
1990 – 1999
- 1999
- [c11]Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451 - 1998
- [j3]Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
Model-adaptable MOSFET parameter-extraction method using an intermediate model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5): 400-405 (1998) - [c10]Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru:
Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD 1998: 537-544 - [c9]Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226 - 1997
- [c8]Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru:
A functional memory type parallel processor for vector quantization. ASP-DAC 1997: 665-666 - [c7]Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
A current mode cyclic A/D converter with a 0.8 μm CMOS process. ASP-DAC 1997: 683-684 - 1996
- [c6]Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI 1996: 154- - 1995
- [c5]Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
A model-adaptable MOSFET parameter extraction system. ASP-DAC 1995 - [c4]Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
An iterative gate sizing approach with accurate delay evaluation. ICCAD 1995: 422-427 - 1993
- [c3]Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru:
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD 1993: 100-103 - 1991
- [c2]Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru:
Branch-and-Bound Placement for Building Block Layout. DAC 1991: 433-439
1980 – 1989
- 1989
- [c1]R. Okuda, Takashi Sato, Hidetoshi Onodera, K. Tamariu:
An efficient algorithm for layout compaction problem with symmetry constraints. ICCAD 1989: 148-151 - 1988
- [j2]Hidetoshi Onodera, Tetsuo Tateishi, Keikichi Tamaru:
A cyclic A/D converter that does not require ratio-matched components. IEEE J. Solid State Circuits 23(1): 152-158 (1988) - 1987
- [j1]Keikichi Tamaru, Hidetoshi Onodera:
System design of a special-purpose computer for LSI design rule checking. Syst. Comput. Jpn. 18(2): 43-54 (1987)
Coauthor Index
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