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2010 – 2019
- 2014
[c9]Matthieu Parizy
, Koichiro Takayama, Yuji Kanazawa:
Software Defect Prediction for LSI Designs. ICSME 2014: 565-568
2000 – 2009
- 2004
- [c8]Praveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama:
High level hardware validation using hierarchical message sequence charts. HLDVT 2004: 167-172 - 2002
- [j4]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita:
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods Syst. Des. 21(1): 95-101 (2002) - [c7]Shuo Sheng, Koichiro Takayama, Michael S. Hsiao:
Effective safety property checking using simulation-based sequential ATPG. DAC 2002: 813-818 - 2001
- [j3]Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama:
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1319-1328 (2001) - [c6]Farzan Fallah, Koichiro Takayama:
A New Functional Test Program Generation Methodology. ICCD 2001: 76-81 - 2000
- [c5]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita:
Automatic partitioning for efficient combinatorial verification. ASP-DAC 2000: 67-72
1990 – 1999
- 1999
- [j2]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
An efficient filter-based approach for combinational verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1542-1557 (1999) - [c4]Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita:
Model Checking Based on Sequential ATPG. CAV 1999: 418-430 - [c3]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137 - 1998
- [c2]Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose:
An approach to verify a large scale system-on-a-chip using symbolic model checking. ICCD 1998: 308-313 - 1990
- [j1]Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato:
A high-speed test-generation method using a test generation circuit. Syst. Comput. Jpn. 21(11): 12-20 (1990)
1980 – 1989
- 1988
- [c1]Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato:
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. ITC 1988: 102-107
Coauthor Index
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