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2010 – 2019
- 2016
[c19]Prab Varma, Miroslav N. Velev
:
Welcome Message. HLDVT 2016: 1- 2012
- [c18]Prab Varma:
Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation. Asian Test Symposium 2012: 233-238
2000 – 2009
- 2004
- [j4]Prab Varma:
Verification evolution or industrial revolution? IEEE Des. Test Comput. 21(2): 168- (2004) - 2003
- [c17]Prab Varma:
Design Verification Problems: Test To The Rescue? ITC 2003: 1292 - 2001
- [c16]Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma:
ATPG for Design Errors-Is It Possible? VTS 2001: 283-285 - 2000
- [j3]Bechir Ayari, Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment. J. Electron. Test. 16(5): 409-418 (2000)
1990 – 1999
- 1998
- [c15]Bechir Ayari, Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment. Asian Test Symposium 1998: 21-26 - [c14]Prab Varma:
System Chip Test Challenges, Are There Solutions Today? (Panel). DAC 1998: 750-751 - [c13]Prab Varma, Sandeep Bhatia:
A structured test re-use methodology for core-based system chips. ITC 1998: 294-302 - [c12]Prab Varma:
System chip test: are we there yet? ITC 1998: 1144 - 1997
- [c11]Sandeep Bhatia, Prab Varma:
Test Compaction in a Parallel Access Scan Environment. Asian Test Symposium 1997: 300-305 - 1996
- [c10]Sandeep Bhatia, Tushar Gheewala, Prab Varma:
A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC 1996: 639-648 - [c9]Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma:
Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503 - 1995
- [c8]Prab Varma:
Optimizing Product Profitability - The Test Way. ITC 1995: 922 - 1994
- [j2]Prab Varma, Tushar Gheewala:
The economics of scan-path design for testability. J. Electron. Test. 5(2-3): 179-193 (1994) - [c7]Prab Varma:
On Path-Delay Testing in a Standard Scan Environment. ITC 1994: 164-173 - 1993
- [c6]Prab Varma, Tushar Gheewala:
Delay Testing Using a Matrix of Accessible Storage. ITC 1993: 243-252 - [c5]Prab Varma:
Scan DFT: Why More Can Cost Less. ITC 1993: 267 - 1992
- [c4]Prab Varma:
On test generation for path delay faults in ASICs. VTS 1992: 19-24 - 1990
- [c3]Prab Varma:
TDRC-a symbolic simulation based design for testability rules checker. ITC 1990: 1055-1064
1980 – 1989
- 1988
- [j1]Prab Varma, Yoshihiro Tohma:
A knowledge-based test generator for standard cell and iterative array logic circuits. IEEE J. Solid State Circuits 23(2): 428-436 (1988) - 1987
- [c2]S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter:
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. DAC 1987: 17-25 - 1984
- [c1]Prab Varma, Anthony P. Ambler, Keith Baker:
An Analysis of the Economics of Self Test. ITC 1984: 20-30
Coauthor Index
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