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ORCIDJonathan Chang
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2023
[c54]Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Atul Katoch, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li:
A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. VLSI Technology and Circuits 2023: 1-2- [c53]Yao-Hung Huang, Yu-Cheng Hsieh, Yu-Cheng Lin, Yue-Der Chih, Eric Wang, Jonathan Chang, Ya-Chin King, Chrong Jung Lin:
High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c52]Victor Sanh, Albert Webson, Colin Raffel, Stephen H. Bach, Lintang Sutawika, Zaid Alyafeai, Antoine Chaffin, Arnaud Stiegler, Arun Raja, Manan Dey, M Saiful Bari, Canwen Xu, Urmish Thakker, Shanya Sharma Sharma, Eliza Szczechla, Taewoon Kim, Gunjan Chhablani, Nihal V. Nayak, Debajyoti Datta, Jonathan Chang, Mike Tian-Jian Jiang, Han Wang, Matteo Manica, Sheng Shen, Zheng Xin Yong, Harshit Pandey, Rachel Bawden, Thomas Wang, Trishala Neeraj, Jos Rozen, Abheesht Sharma, Andrea Santilli, Thibault Févry, Jason Alan Fries, Ryan Teehan, Teven Le Scao, Stella Biderman, Leo Gao, Thomas Wolf, Alexander M. Rush:
Multitask Prompted Training Enables Zero-Shot Task Generalization. ICLR 2022 - [c51]Jae-Gyung Ahn, Jim Wesselkamper, Ryan S. W. Baek, Ping-Chin Yeh, Jonathan Chang, Jennifer Wong, Xin Wu:
Reliability Analysis of Physically Unclonable Function by Using Aging Variability Simulation. IRPS 2022: 1 - [c50]Yen-Kang Fu, Jonathan Chang, David Jao:
Optimal Generic Attack Against Basic Boneh-Boyen Signatures. ISPEC 2022: 505-519 - [c49]Nail Etkin Can Akkaya, Gary Chan, Hung-Jen Liao, Yih Wang
, Jonathan Chang:
A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology. VLSI Technology and Circuits 2022: 110-111 - 2021
- [b1]Jonathan Chang:
Computational Framework for the Identification of Neural Circuits Underlying Psychiatric Disorders. Columbia University, USA, 2021 - [j15]Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang:
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. IEEE J. Solid State Circuits 56(1): 188-198 (2021) - [j14]Daniel Carranza, Jonathan Chang, Chris Kapulkin, Ryan Sandford:
2-adjoint equivalences in homotopy type theory. Log. Methods Comput. Sci. 17(1) (2021) - [c48]Jae-Gyung Ahn, Rhesa Nathanael, I-Ru Chen, Ping-Chin Yeh, Jonathan Chang:
Product Lifetime Estimation in 7nm with Large data of Failure Rate and Si-Based Thermal Coupling Model. IRPS 2021: 1-6 - [c47]Eric Karl, Shinichiro Shiratake, Jonathan Chang:
Session 24 Overview: Advanced Embedded Memories Memory Subcommittee. ISSCC 2021: 332-333 - [c46]Hidehiro Fujiwara, Yi-Hsin Nien, Chih-Yu Lin, Hsien-Yu Pan, Hao-Wen Hsu, Shin-Rung Wu, Yao-Yi Liu, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang:
A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue. ISSCC 2021: 340-342 - [c45]Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag:
SE1: What Technologies Will Shape the Future of Computing? ISSCC 2021: 537-538 - [c44]Shaun Chou, Gu-Huan Li, Shawn Chen, Jun-Hao Chang, Wan-Hsueh Cheng, Shao-Ding Wu, Philex Fan, Chia-En Huang, Yu-Der Chih, Yih Wang, Jonathan Chang:
A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing. VLSI Circuits 2021: 1-2 - [i4]Victor Sanh, Albert Webson, Colin Raffel, Stephen H. Bach, Lintang Sutawika, Zaid Alyafeai, Antoine Chaffin, Arnaud Stiegler, Teven Le Scao, Arun Raja, Manan Dey, M. Saiful Bari, Canwen Xu, Urmish Thakker, Shanya Sharma, Eliza Szczechla, Taewoon Kim, Gunjan Chhablani, Nihal V. Nayak, Debajyoti Datta, Jonathan Chang, Mike Tian-Jian Jiang, Han Wang, Matteo Manica, Sheng Shen, Zheng Xin Yong, Harshit Pandey, Rachel Bawden, Thomas Wang, Trishala Neeraj, Jos Rozen, Abheesht Sharma, Andrea Santilli, Thibault Févry, Jason Alan Fries, Ryan Teehan, Stella Biderman, Leo Gao, Tali Bers, Thomas Wolf, Alexander M. Rush:
Multitask Prompted Training Enables Zero-Shot Task Generalization. CoRR abs/2110.08207 (2021) - 2020
- [c43]Jae-Gyung Ahn, Ping-Chin Yeh, Jonathan Chang:
Estimation of Product Reliability using TDDB Simulation and Statistical EM Method. IRPS 2020: 1-6 - [c42]Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li:
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. ISSCC 2020: 238-240 - [c41]Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang:
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. ISSCC 2020: 242-244
2010 – 2019
- 2019
- [j13]Yu-Fan Chiang, Wei-Yu Chien, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King:
FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems. Integr. 65: 97-103 (2019) - [j12]Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang:
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell. IEEE J. Solid State Circuits 54(4): 1152-1160 (2019) - [j11]Chien-Ping Wang, Ying-Chun Shen, Peng-Chun Liou, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King:
Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology. Sensors 19(7): 1585 (2019) - [c40]Jae-Gyung Ahn, I-Ru Chen, Ping-Chin Yeh, Jonathan Chang:
Design-For-Reliability Flow in 7nm Products with Data Center and Automotive Applications. IRPS 2019: 1-5 - [c39]Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin, Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang:
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. ISSCC 2019: 390-392 - [c38]Shih-Lien Lu, Cheng-En Lee, Peter Noel, Saman Adham, Ted Wong, Jonathan Chang:
A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering. VLSI-DAT 2019: 1-4 - [i3]Jonathan Chang, Nishanth Kumar, Sean Hastings, Aaron Gokaslan, Diego Romeres, Devesh K. Jha, Daniel Nikovski, George Dimitri Konidaris, Stefanie Tellex:
Learning Deep Parameterized Skills from Demonstration for Re-targetable Visuomotor Control. CoRR abs/1910.10628 (2019) - 2018
- [c37]Jae-Gyung Ahn, Ping-Chin Yeh, Jonathan Chang:
Electromigration failure rate of redundant via. IRPS 2018: 1 - [c36]Jonathan Chang, Chun Shiah, Leland Chang:
Session 11 overview: SRAM: Memory subcommittee. ISSCC 2018: 194-195 - [c35]Michael Clinton, Rajinder Singh, Marty Tsai, Shayan Zhang, Bryan Sheffield, Jonathan Chang:
A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications. ISSCC 2018: 200-201 - [c34]Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang:
A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology. VLSI Circuits 2018: 13-14 - [c33]Deepayan Chakrabarti, Stanislav Funiak, Jonathan Chang, Sofus A. Macskassy:
Joint Label Inference in Networks. WWW (Companion Volume) 2018: 483-487 - 2017
- [j10]Deepayan Chakrabarti, Stanislav Funiak, Jonathan Chang, Sofus A. Macskassy:
Joint Label Inference in Networks. J. Mach. Learn. Res. 18: 59:1-59:39 (2017) - [c32]Jonathan Chang, Stefan Scherer:
Learning representations of emotional speech with deep convolutional generative adversarial networks. ICASSP 2017: 2746-2750 - [c31]Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu:
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. ISSCC 2017: 206-207 - [c30]Michael Clinton, Hank Cheng, Hung-Jen Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang:
12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. ISSCC 2017: 210-211 - [c29]Martin Brox, Jonathan Chang, Howard C. Luong, Paul Liang, Riccardo Mariani:
EE5: When will we stop driving our cars? ISSCC 2017: 524 - [i2]Jonathan Chang, Stefan Scherer:
Learning Representations of Emotional Speech with Deep Convolutional Generative Adversarial Networks. CoRR abs/1705.02394 (2017) - 2016
- [c28]Hidehiro Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, Dar Sun, Shin-Rung Wu, Hung-Jen Liao, Jonathan Chang:
A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications. A-SSCC 2016: 185-188 - [c27]Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang:
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. VLSI Circuits 2016: 1-2 - 2015
- [j9]Vivek De, Stephen Kosonocky, Jonathan Chang, Yogesh K. Ramadass, David Stoppa:
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions. IEEE J. Solid State Circuits 50(1): 4-9 (2015) - [j8]Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang:
A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. IEEE J. Solid State Circuits 50(1): 170-177 (2015) - [c26]Jae-Gyung Ahn, Ming Feng Lu, Nitin Navale, Dawn Graves, Ping-Chin Yeh, Jonathan Chang, S. Y. Pai:
Product-level reliability estimator with budget-based reliability management in 20nm technology. IRPS 2015: 6 - [c25]Jonathan Chang, Leland Chang, Antoine Dupret, Chulwoo Kim, Fatih Hamzaoglu, Takefumi Yoshikawa:
F2: Memory trends: From big data to wearable devices. ISSCC 2015: 1-2 - [c24]Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang:
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies. ISSCC 2015: 1-3 - 2014
- [c23]Ching-Wei Wu, Ming-Hung Chang, Chia-Cheng Chen, Robin Lee, Hung-Jen Liao, Jonathan Chang:
A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS. A-SSCC 2014: 145-148 - [c22]Deepayan Chakrabarti, Stanislav Funiak, Jonathan Chang, Sofus A. Macskassy:
Joint Inference of Multiple Label Types in Large Networks. ICML 2014: 874-882 - [c21]Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang:
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. ISSCC 2014: 238-239 - [c20]Yusuke Oike, Makoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jonathan Chang, Tadahiro Kuroda:
F2: 3D stacking technologies for image sensors and memories. ISSCC 2014: 512-513 - [c19]Saman Adham, Jonathan Chang, Hung-Jen Liao, John Hung, Ting-Hua Hsieh:
The importance of DFX, a foundry perspective. ITC 2014: 1-6 - [i1]Deepayan Chakrabarti, Stanislav Funiak, Jonathan Chang, Sofus A. Macskassy:
Joint Inference of Multiple Label Types in Large Networks. CoRR abs/1401.7709 (2014) - 2013
- [c18]Jonathan Chang, Yen-Huei Chen, Hank Cheng, Wei-Min Chan, Hung-Jen Liao, Quincy Li, Stanley Chang, Sreedhar Natarajan, Robin Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, George H. Chang:
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications. ISSCC 2013: 316-317 - 2012
- [c17]Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, Hong-Jen Liao, Jonathan Chang:
A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays. VLSIC 2012: 64-65 - 2011
- [c16]Jonathan Chang, Eric Sun:
Location3: How Users Share and Respond to Location-Based Data on Social. ICWSM 2011 - 2010
- [j7]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE J. Solid State Circuits 45(1): 7-14 (2010) - [c15]Jonathan Chang, Karon E. MacLean, Steve Yohanan:
Gesture Recognition in the Haptic Creature. EuroHaptics (1) 2010: 385-391 - [c14]Jonathan Chang, Itamar Rosenn, Lars Backstrom, Cameron Marlow:
ePluribus: Ethnicity on Social Networks. ICWSM 2010 - [c13]Cheolmin Park, Roy Badeau, Larry Biro, Jonathan Chang, Tejpal Singh, Jim Vash, Bo Wang, Tom Wang:
A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor. ISSCC 2010: 180-181 - [c12]Jonathan Chang:
Not-So-Latent Dirichlet Allocation: Collapsed Gibbs Sampling Using Human Judgments. Mturk@HLT-NAACL 2010: 131-138
2000 – 2009
- 2009
- [c11]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
Power reduction techniques for an 8-core xeon® processor. ESSCIRC 2009: 340-343 - [c10]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli:
A 45nm 8-core enterprise Xeon® processor. ISSCC 2009: 56-57 - [c9]Matthew Black, Jeannette N. Chang, Jonathan Chang, Shrikanth S. Narayanan:
Comparison of child-human and child-computer interactions based on manual annotations. WOCCI 2009: 49-54 - 2007
- [j6]David I. August, Jonathan Chang, Sylvain Girbal, Daniel Gracia Pérez, Gilles Mouchard, David A. Penry, Olivier Temam, Neil Vachharajani:
UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development. IEEE Comput. Archit. Lett. 6(2): 45-48 (2007) - [j5]Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits 42(1): 17-25 (2007) - [j4]Jonathan Chang, Ming Huang, Jonathan Shoemaker, John Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, Raghuraman Ganesan, Gloria Leong, Venkata Lukka, Stefan Rusu, Durgesh Srivastava:
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. IEEE J. Solid State Circuits 42(4): 846-852 (2007) - [j3]George A. Reis, Jonathan Chang, David I. August:
Automatic Instruction-Level Software-Only Recovery. IEEE Micro 27(1): 36-47 (2007) - 2006
- [c8]Bolei Guo, Youfeng Wu, Cheng Wang, Matthew J. Bridges, Guilherme Ottoni, Neil Vachharajani, Jonathan Chang, David I. August:
Selective Runtime Memory Disambiguation in a Dynamic Binary Translator. CC 2006: 65-79 - [c7]Jonathan Chang, George A. Reis, David I. August:
Automatic Instruction-Level Software-Only Recovery. DSN 2006: 83-92 - [c6]Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang:
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. ISSCC 2006: 315-324 - 2005
- [j2]Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni:
A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. IEEE J. Solid State Circuits 40(1): 195-203 (2005) - [j1]George A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David I. August, Shubhendu S. Mukherjee:
Software-controlled fault tolerance. ACM Trans. Archit. Code Optim. 2(4): 366-396 (2005) - [c5]George A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David I. August:
SWIFT: Software Implemented Fault Tolerance. CGO 2005: 243-254 - [c4]George A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David I. August, Shubhendu S. Mukherjee:
Design and Evaluation of Hybrid Fault-Detection Systems. ISCA 2005: 148-159 - 2004
- [c3]Neil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, David I. August:
RIFLE: An Architectural Framework for User-Centric Information-Flow Security. MICRO 2004: 243-254 - 2003
- [c2]Alain J. Martin, Mika Nyström, Karl Papadantonakis, Paul I. Pénzes, Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, Ahmet Tura:
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller. ASYNC 2003: 14-23
1990 – 1999
- 1996
- [c1]Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell:
Analysis and Detection of Timing Failures in an Experimental Test Chip. ITC 1996: 691-700
Coauthor Index
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