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2020 – today
- 2023
[c4]En-Jui Chang, Cheng-Xin Xue, Chetan Deshpande, Gajanan Jedhe, Jenwei Liang, Chih-Chung Cheng, Hung-Wei Lin, Chia-Da Lee, Sushil Kumar, Kim Soon Jway, Zijie Guo, Ritesh Garg, Allen-Cl Lu, Chien-Hung Lin, Meng-Han Hsieh, Tsung-Yao Lin, Chih-Cheng Chen:
A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision. VLSI Technology and Circuits 2023: 1-2- [c3]Gajanan Jedhe, Chetan Deshpande, Sushil Kumar, Cheng-Xin Xue, Zijie Guo, Ritesh Garg, Kim Soon Jway, En-Jui Chang, Jenwei Liang, Zhe Wan, Zhenhao Pan:
A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications. VLSI Technology and Circuits 2023: 1-2 - 2021
- [c2]Chetan Deshpande, Ritesh Garg, Gajanan Jedhe, Gaurang Narvekar, Sushil Kumar:
A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry Update Capability for Data Center ASICs. VLSI Circuits 2021: 1-2
2000 – 2009
- 2008
- [c1]Ritesh Garg, Richard Putman, Nur A. Touba:
Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. VTS 2008: 35-42
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