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2020 – today
- 2024
[j68]Yuqing Ren
, Hassan Harb, Yifei Shen, Alexios Balatsoukas-Stimming, Andreas Burg:
A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2911-2924 (2024)- [j67]Naci Pekcokguler, Hung-Chi Han, Dominique Morche, Catherine Dehollain, Andreas Burg, Christian C. Enz:
Analytical Modeling of Short-Channel MOSFET Differential Pair Non-Linearity. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4411-4419 (2024) - [j66]Naci Pekcokguler, Dominique Morche, Andreas Burg, Catherine Dehollain:
A High Dynamic Range Envelop Detector for Heterodyne Receiver Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1929-1933 (2024) - [j65]Yuqing Ren, Yifei Shen, Leyu Zhang, Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Emmanuel Boutillon, Andreas Burg, Chuan Zhang:
High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes. IEEE Trans. Signal Process. 72: 1158-1174 (2024) - [c171]Leyu Zhang, Yuqing Ren, Yifei Shen, Wuyang Zhou, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg:
A Low-Latency and High-Performance SCL Decoder with Frame-Interleaving. ISCAS 2024: 1-5 - [c170]Andreas Toftegaard Kristensen, Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg:
Monostatic Multi-Target Wi-Fi-Based Breathing Rate Sensing Using Openwifi. WCNC 2024: 1-6 - [i43]Yuqing Ren, Leyu Zhang, Ludovic Damien Blanc, Yifei Shen, Xinwei Li, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg:
A Node-Based Polar List Decoder with Frame Interleaving and Ensemble Decoding Support. CoRR abs/2408.04334 (2024) - 2023
- [j64]Naci Pekcokguler, Dominique Morche, Andreas Burg, Catherine Dehollain:
An Ultra-Low-Power Widely-Tunable Complex Band-Pass Filter for RF Spectrum Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3879-3887 (2023) - [c169]Joachim Tapparel, Andreas Burg:
Increasing LoRa Sensitivity and Reliability with an IoT Cloud RAN. ACSSC 2023: 197-201 - [c168]Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg:
Single-Anchor UWB Localization Using Channel Impulse Response Distributions. ICASSP 2023: 1-5 - [c167]Yifei Shen, Yuqing Ren, Andreas Toftegaard Kristensen, Xiaohu You, Chuan Zhang, Andreas Burg:
Improved Belief Propagation Decoding of Turbo Codes. ICASSP 2023: 1-5 - [c166]Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg:
Band-of-Interest-Based Channel Impulse Response Fusion for Breathing Rate Estimation with UWB. ICC Workshops 2023: 1695-1700 - [c165]Yifei Shen, Yuqing Ren, Andreas Burg:
Iterative Ordered Statistics Decoding of Product Codes. ISTC 2023: 1-5 - [c164]Yuqing Ren, Yifei Shen, Emmanuel Boutillon, Alexios Balatsoukas-Stimming, Andreas Burg:
Design of Concatenated Product Codes with Spatially-Coupled LDPC Codes. ISWCS 2023: 1-6 - [c163]Joonas Valkama, Mehdi Safarpour, Håkan Dicander, Zhongmin Deng, Andreas Burg, Olli Silvén:
Low Power LDPC Decoding by Reliable Voltage Down-Scaling. NorCAS 2023: 1-5 - [c162]Joachim Tapparel, Alexios Balatsoukas-Stimming, Andreas Burg:
LoRa Preamble Detection Robust to Inter-channel Interference. SPAWC 2023: 516-520 - [c161]Yaya Etiabi, Mohammed Jouhari, Andreas Burg, El Mehdi Amhoud:
Spreading Factor assisted LoRa Localization with Deep Reinforcement Learning. VTC2023-Spring 2023: 1-5 - [i42]Yuqing Ren, Hassan Harb, Yifei Shen, Alexios Balatsoukas-Stimming, Andreas Burg:
A High-Performance and Low-Complexity 5G LDPC Decoder: Algorithm and Implementation. CoRR abs/2310.15801 (2023) - 2022
- [j63]Reza Ghanaatian, Marco Widmer, Andreas Burg:
Design for Test With Unreliable Memories by Restoring the Beauty of Randomness. IEEE Des. Test 39(2): 112-120 (2022) - [j62]Mathieu Xhonneux, Joachim Tapparel, Alexios Balatsoukas-Stimming, Andreas Burg, Orion Afisiadis:
A Maximum-Likelihood-Based Two-User Receiver for LoRa Chirp Spread-Spectrum Modulation. IEEE Internet Things J. 9(22): 22993-23007 (2022) - [j61]Yuqing Ren, Andreas Toftegaard Kristensen, Yifei Shen, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg:
A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation. IEEE Trans. Signal Process. 70: 5592-5607 (2022) - [j60]Yifei Shen, Alexios Balatsoukas-Stimming, Xiaohu You, Chuan Zhang, Andreas Peter Burg:
Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes. IEEE Wirel. Commun. Lett. 11(2): 391-395 (2022) - [c160]Zongyao Li, Leyu Zhang, Yifei Shen, Andreas Burg, Xiaohu You, Chuan Zhang:
List Ordered Statistics Decoders for Polar Codes. IEEECONF 2022: 628-633 - [c159]Adrian Schumacher, Ruben Merz, Andreas Burg:
Increasing Cellular Network Energy Efficiency for Railway Corridors. DATE 2022: 1103-1106 - [c158]Yifei Shen, Yuqing Ren, Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Xiaohu You, Chuan Zhang, Andreas Peter Burg:
Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes. ICC 2022: 116-122 - [c157]Sitian Li, Alexios Balatsoukas-Stimming, Andreas Burg:
Device-free Movement Tracking using the UWB Channel Impulse Response with Machine Learning. SPAWC 2022: 1-5 - [c156]Adrian Schumacher, Ruben Merz, Andreas Burg:
Beam Selection and Tracking for Amplify-and-Forward Repeaters. VTC Spring 2022: 1-7 - [i41]Yuqing Ren, Andreas Toftegaard Kristensen, Yifei Shen, Alexios Balatsoukas-Stimming, Chuan Zhang, Andreas Burg:
A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation. CoRR abs/2205.08857 (2022) - [i40]Adrian Schumacher, Ruben Merz, Andreas Burg:
Increasing Cellular Network Energy Efficiency for Railway Corridors. CoRR abs/2205.11808 (2022) - [i39]Yuqing Ren, Yifei Shen, Leyu Zhang, Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Andreas Burg, Chuan Zhang:
High-Throughput Flexible Belief Propagation List Decoder for Polar Codes. CoRR abs/2210.13887 (2022) - 2021
- [j59]Adrian Schumacher, Ruben Merz, Andreas Burg:
Adding Indoor Capacity without Fiber Backhaul: An mmWave Bridge Prototype. IEEE Commun. Mag. 59(4): 110-115 (2021) - [j58]Orion Afisiadis, Sitian Li, Joachim Tapparel, Andreas Burg, Alexios Balatsoukas-Stimming:
On the Advantage of Coherent LoRa Detection in the Presence of Interference. IEEE Internet Things J. 8(14): 11581-11593 (2021) - [j57]Joachim Tapparel, Mathieu Xhonneux, David Bol, Jérôme Louveaux, Andreas Burg:
Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers. IEEE Open J. Commun. Soc. 2: 2725-2738 (2021) - [j56]Flavio Ponzina, Miguel Peón Quirós, Andreas Burg, David Atienza:
E2CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices. IEEE Trans. Computers 70(8): 1199-1212 (2021) - [j55]Mohammad Rowshan, Andreas Burg, Emanuele Viterbo:
Polarization-Adjusted Convolutional (PAC) Codes: Sequential Decoding vs List Decoding. IEEE Trans. Veh. Technol. 70(2): 1434-1447 (2021) - [c155]Mathieu Xhonneux, Joachim Tapparel, Péter Scheepers, Orion Afisiadis, Alexios Balatsoukas-Stimming, David Bol, Jérôme Louveaux, Andreas Burg:
A Two-User Successive Interference Cancellation LoRa Receiver with Soft-Decoding. ACSCC 2021: 948-953 - [c154]Roberto La Rosa, Mario Costanza, Andreas Burg, Catherine Dehollain, Patrizia Livreri:
Intrinsically Self-powered, Battery-free, and Sensor-free Ambient Light Control System. IEEE SENSORS 2021: 1-4 - [c153]Naci Pekcokguler, Dominique Morche, Adrian Frischknecht, Christoph Gerum, Andreas Burg, Catherine Dehollain:
Dynamic Range and Complexity Optimization of Mixed-Signal Machine Learning Systems. ISCAS 2021: 1-5 - [c152]Naci Pekcokguler, Mickael Maman, Andreas Burg, Catherine Dehollain, Dominique Morche:
A Novel RF Spectrum Monitoring Architecture for an Ultra-Low-Power Wi-Fi Geopositioning System. NEWCAS 2021: 1-4 - [c151]Adrian Schumacher, Nima Jamaly, Ruben Merz, Andreas Burg:
Improving railway track coverage with mmWave bridges: A Measurement Campaign. 5G-MeMZ@SIGCOMM 2021: 8-13 - [c150]Sitian Li, Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming:
ComplexBeat: Breathing Rate Estimation from Complex CSI. SiPS 2021: 217-222 - [i38]Arthur Gassner, Claudiu Musat, Alexandru Rusu, Andreas Burg:
OpenCSI: An Open-Source Dataset for Indoor Localization Using CSI-Based Fingerprinting. CoRR abs/2104.07963 (2021) - [i37]Adrian Schumacher, Ruben Merz, Andreas Burg:
3.5 GHz Coverage Assessment with a 5G Testbed. CoRR abs/2105.06812 (2021) - [i36]Adrian Schumacher, Ruben Merz, Andreas Burg:
A mmWave Bridge Concept to Solve the Cellular Outdoor-to-Indoor Challenge. CoRR abs/2105.06885 (2021) - [i35]Adrian Schumacher, Ruben Merz, Andreas Burg:
Adding Indoor Capacity Without Fiber Backhaul: A mmWave Bridge Prototype. CoRR abs/2105.06911 (2021) - 2020
- [j54]Benoît W. Denkinger, Flavio Ponzina, Soumya Basu, Andrea Bonetti, Szabolcs Balási, Martino Ruggiero, Miguel Peón Quirós, Davide Rossi, Andreas Burg, David Atienza:
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices. IEEE Des. Test 37(2): 84-92 (2020) - [j53]Chuan Zhang, Yeong-Luh Ueng, Christoph Studer, Andreas Burg:
Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(2): 145-148 (2020) - [j52]Chuan Zhang, Yeong-Luh Ueng, Christoph Studer, Andreas Burg:
Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(2): 149-163 (2020) - [j51]Yann Kurzo, Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming:
Hardware Implementation of Neural Self-Interference Cancellation. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(2): 204-216 (2020) - [j50]Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf:
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits 55(1): 38-48 (2020) - [j49]Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg:
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1207-1217 (2020) - [j48]Michael Meidlinger, Gerald Matz, Andreas Burg:
Design and Decoding of Irregular LDPC Codes Based on Discrete Message Passing. IEEE Trans. Commun. 68(3): 1329-1343 (2020) - [j47]Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg:
Gain-Cell Embedded DRAMs: Modeling and Design Space. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 646-659 (2020) - [j46]Orion Afisiadis, Matthieu Cotting, Andreas Burg, Alexios Balatsoukas-Stimming:
On the Error Rate of the LoRa Modulation With Interference. IEEE Trans. Wirel. Commun. 19(2): 1292-1304 (2020) - [c149]Andreas Toftegaard Kristensen, Alexios Balatsoukas-Stimming, Andreas Burg:
On the Implementation Complexity of Digital Full-Duplex Self-Interference Cancellation. ACSSC 2020: 969-973 - [c148]Mathieu Xhonneux, Joachim Tapparel, Orion Afisiadis, Alexios Balatsoukas-Stimming, Andreas Burg:
A Maximum-Likelihood-based Multi-User LoRa Receiver Implemented in GNU Radio. ACSSC 2020: 1106-1111 - [c147]Andreas Toftegaard Kristensen, Robert Giterman, Alexios Balatsoukas-Stimming, Andreas Burg:
Lupulus: A Flexible Hardware Accelerator for Neural Networks. ICASSP 2020: 1608-1612 - [c146]Orion Afisiadis, Andreas Burg, Alexios Balatsoukas-Stimming:
Coded LoRa Frame Error Rate Analysis. ICC 2020: 1-6 - [c145]Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming:
Identification of Non-Linear RF Systems using Backpropagation. ICC Workshops 2020: 1-6 - [c144]Sitian Li, Andreas Burg, Alexios Balatsoukas-Stimming:
Training Channel Selection for Learning-Based 1-Bit Precoding in Massive MU-MIMO. ICC Workshops 2020: 1-6 - [c143]Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg:
Gain-Cell Embedded DRAMs: Modeling and Design Space. ISCAS 2020: 1 - [c142]Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman:
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. ISCAS 2020: 1 - [c141]Mohammad Rowshan, Andreas Burg, Emanuele Viterbo:
Complexity-efficient Fano Decoding of Polarization-adjusted Convolutional (PAC) Codes. ISITA 2020: 200-204 - [c140]Ning Xu, Sitian Li, Clement Serge Charollais, Andreas Burg, Adrian Schumacher:
Machine Learning Based Outdoor Localization using the RSSI of Multibeam Antennas. SiPS 2020: 1-5 - [c139]Joachim Tapparel, Orion Afisiadis, Paul Mayoraz, Alexios Balatsoukas-Stimming, Andreas Burg:
An Open-Source LoRa Physical Layer Prototype on GNU Radio. SPAWC 2020: 1-5 - [c138]Adrian Schumacher, Ruben Merz, Andreas Burg:
A mmWave Bridge Concept to Solve the Cellular Outdoor-to-Indoor Challenge. VTC Spring 2020: 1-6 - [i34]Yann Kurzo, Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming:
Hardware Implementation of Neural Self-Interference Cancellation. CoRR abs/2001.04543 (2020) - [i33]Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming:
Identification of Non-Linear RF Systems Using Backpropagation. CoRR abs/2001.09877 (2020) - [i32]Mohammad Rowshan, Andreas Burg, Emanuele Viterbo:
Polarization-adjusted Convolutional (PAC) Codes: Fano Decoding vs List Decoding. CoRR abs/2002.06805 (2020) - [i31]Andreas Toftegaard Kristensen, Robert Giterman, Alexios Balatsoukas-Stimming, Andreas Burg:
Lupulus: A Flexible Hardware Accelerator for Neural Networks. CoRR abs/2005.01016 (2020)
2010 – 2019
- 2019
- [j45]Andreas Burg, Matthew M. Ziegler, Saibal Mukhopdhyay:
Conference Report from the 2019 International Symposium on Low Power Electronics and Design (ISLPED). IEEE Des. Test 36(6): 82-83 (2019) - [j44]Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman:
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 2042-2046 (2019) - [j43]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [j42]Emmanuel Boutillon, Andreas Burg:
Editor's Note: Special Issue on Design and Implementation of Signal Processing Systems. J. Signal Process. Syst. 91(9): 979 (2019) - [c137]Andreas Toftegaard Kristensen, Andreas Burg, Alexios Balatsoukas-Stimming:
Advanced Machine Learning Techniques for Self-Interference Cancellation in Full-Duplex Radios. ACSSC 2019: 1149-1153 - [c136]Orion Afisiadis, Matthieu Cotting, Andreas Burg, Alexios Balatsoukas-Stimming:
LoRa Symbol Error Rate Under Non-Aligned Interference. ACSSC 2019: 1957-1961 - [c135]Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici:
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. A-SSCC 2019: 219-222 - [c134]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici:
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC 2019: 239-240 - [c133]Marc Pons, Christoph Thomas Müller, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi:
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS. CICC 2019: 1-4 - [c132]Marco Widmer, Andrea Bonetti, Andreas Burg:
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems. DAC 2019: 36 - [c131]Reza Ghanaatian, Orion Afisiadis, Matthieu Cotting, Andreas Burg:
Lora Digital Receiver Analysis and Implementation. ICASSP 2019: 1498-1502 - [c130]Ester Vicario Bravo, Andrea Bonetti, Andreas Burg:
Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space. ISCAS 2019: 1-5 - [c129]Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici:
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC 2019: 476-478 - [c128]Reza Ghanaatian, Vahid Jamali, Andreas Burg, Robert Schober:
Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems. PIMRC 2019: 1-7 - [c127]Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici:
JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. PRIME 2019: 101-104 - [c126]Christoph Thomas Müller, Marc Pons, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi:
Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC. PRIME 2019: 285-288 - [c125]Adrian Schumacher, Ruben Merz, Andreas Burg:
3.5 GHz Coverage Assessment with a 5G Testbed. VTC Spring 2019: 1-6 - [i30]Orion Afisiadis, Matthieu Cotting, Andreas Burg, Alexios Balatsoukas-Stimming:
LoRa Symbol Error Rate Under Non-Chip- and Non-Phase-Aligned Interference. CoRR abs/1905.00439 (2019) - 2018
- [j41]Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman:
An 800-MHz Mixed- VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications. IEEE J. Solid State Circuits 53(7): 2136-2148 (2018) - [j40]Andreas Burg, Anupam Chattopadhyay, Kwok-Yan Lam:
Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things. Proc. IEEE 106(1): 38-60 (2018) - [j39]Robert Giterman, Alexander Fish, Andreas Burg, Adam Teman:
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1245-1256 (2018) - [j38]Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl:
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3529-3542 (2018) - [j37]Alexios Balatsoukas-Stimming, Andreas Burg:
Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel. IEEE Trans. Commun. 66(6): 2322-2332 (2018) - [j36]Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg:
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 329-340 (2018) - [c124]Yann Kurzo, Andreas Burg, Alexios Balatsoukas-Stimming:
Design and Implementation of a Neural Network Aided Self-Interference Cancellation Scheme for Full-Duplex Radios. ACSSC 2018: 589-593 - [c123]Andrea Bonetti, Jeremy Constantin, Adam Ternan, Andreas Burg:
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. ISCAS 2018: 1-4 - [c122]Pascal Giard, Alexios Balatsoukas-Stimming, Andreas Burg:
On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes. ISTC 2018: 1-5 - [c121]Pascal Giard, Andreas Burg:
Fast-SSC-flip decoding of polar codes. WCNC Workshops 2018: 73-77 - [i29]Pascal Giard, Alexios Balatsoukas-Stimming, Andreas Burg:
On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes. CoRR abs/1807.00655 (2018) - [i28]Reza Ghanaatian, Vahid Jamali, Andreas Burg, Robert Schober:
Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems. CoRR abs/1811.04138 (2018) - [i27]Reza Ghanaatian, Orion Afisiadis, Matthieu Cotting, Andreas Burg:
LoRa Digital Receiver Analysis and Implementation. CoRR abs/1811.04146 (2018) - 2017
- [j35]Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse:
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test 34(6): 46-53 (2017) - [j34]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg:
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 616-629 (2017) - [j33]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini:
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j32]Andrea Bonetti, Adam Teman, Philippe Flatresse, Andreas Burg:
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2388-2400 (2017) - [j31]Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg:
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. ACM Trans. Design Autom. Electr. Syst. 22(4): 62:1-62:20 (2017) - [j30]Jeremy Constantin, Raphaël Houlmann, Nicholas Preyss, Nino Walenta, Hugo Zbinden, Pascal Junod, Andreas Burg:
An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems. J. Signal Process. Syst. 86(1): 1-15 (2017) - [c120]Orion Afisiadis, Andrew Charles Mallory Austin, Alexios Balatsoukas-Stimming, Andreas Burg:
Full-duplex communications for wireless links with asymmetric capacity requirements. ACSSC 2017: 1682-1686 - [c119]Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman:
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. ESSCIRC 2017: 308-311 - [c118]Andrew Charles Mallory Austin, Orion Afisiadis, Andreas Burg:
Digital predistortion of hardware impairments for full-duplex transceivers. GlobalSIP 2017: 878-882 - [c117]Reza Ghanaatian, Andreas Burg:
DVFS based power management for LDPC decoders with early termination. SiPS 2017: 1-6 - [c116]Pascal Giard, Alexios Balatsoukas-Stimming, Andreas Burg:
Blind detection of polar codes. SiPS 2017: 1-6 - [c115]Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg:
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders. WCNC Workshops 2017: 1-6 - [i26]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross:
A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code. CoRR abs/1702.00938 (2017) - [i25]Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg:
Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders. CoRR abs/1702.04707 (2017) - [i24]Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg:
A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing. CoRR abs/1703.05769 (2017) - [i23]Pascal Giard, Alexios Balatsoukas-Stimming, Andreas Burg:
Blind Detection of Polar Codes. CoRR abs/1705.02111 (2017) - [i22]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg:
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. CoRR abs/1708.09603 (2017) - [i21]Pascal Giard, Andreas Burg:
Fast-SSC-Flip Decoding of Polar Codes. CoRR abs/1712.00256 (2017) - 2016
- [j29]Noa Edri, Pascal Meinerzhagen, Adam Teman, Andreas Burg, Alexander Fish:
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 222-232 (2016) - [j28]Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues:
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(6): 806-817 (2016) - [j27]Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg:
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. ACM Trans. Design Autom. Electr. Syst. 21(4): 59:1-59:25 (2016) - [j26]Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish:
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 358-362 (2016) - [j25]Christian Senning, Georgios Karakonstantis, Andreas Burg:
Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems. J. Signal Process. Syst. 85(1): 129-142 (2016) - [c114]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross:
A multi-Gbps unrolled hardware list decoder for a systematic polar code. ACSSC 2016: 1194-1198 - [c113]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini:
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c112]Hazar Yueksel, Giovanni Cherubini, Roy D. Cideciyan, Simeon Furrer, Andreas Burg, Thomas Toifl:
High-speed link with trellis-coded modulation and Reed-Solomon coding. CSCN 2016: 231-236 - [c111]Jeremy Constantin, Andreas Peter Burg, Zheng Wang, Anupam Chattopadhyay, Georgios Karakonstantis:
Statistical fault injection for impact-evaluation of timing errors on application performance. DAC 2016: 13:1-13:6 - [c110]Loris Duch, Pablo García Del Valle, Shrikanth Ganapathy, Andreas Burg, David Atienza:
Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices. DATE 2016: 838-841 - [c109]Andreas Peter Burg:
Approximate computing for unreliable silicon. DTIS 2016: 1 - [c108]Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg:
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. ESSCIRC 2016: 261-264 - [c107]Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl:
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. ESSCIRC 2016: 309-312 - [c106]Hazar Yueksel, Giovanni Cherubini, Roy D. Cideciyan, Andreas Burg, Thomas Toifl:
Design considerations on sliding-block viterbi detectors for high-speed data transmission. ICSPCS 2016: 1-6 - [c105]Nicholas Preyss, Andreas Burg:
Experimental signal-quality characterization of a high-capacity mmWave link for backhaul applications. SAM 2016: 1-5 - [c104]Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Peter Burg, Claude Thibeault, Warren J. Gross:
Hardware decoders for polar codes: An overview. ISCAS 2016: 149-152 - [c103]Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg:
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. ISCAS 2016: 1006-1009 - [c102]Reza Ghanaatian, Paul N. Whatmough, Jeremy Constantin, Adam Teman, Andreas Burg:
A low-power correlator for wakeup receivers with algorithm pruning through early termination. ISCAS 2016: 2667-2670 - [c101]Andrew Charles Mallory Austin, Alexios Balatsoukas-Stimming, Andreas Peter Burg:
Digital predistortion of power amplifier non-linearities for full-duplex transceivers. SPAWC 2016: 1-5 - [c100]Orion Afisiadis, Andrew Charles Mallory Austin, Alexios Balatsoukas-Stimming, Andreas Burg:
Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency. VTC Spring 2016: 1-5 - [i20]Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Burg, Claude Thibeault, Warren J. Gross:
Hardware Decoders for Polar Codes: An Overview. CoRR abs/1606.00737 (2016) - [i19]Mohsen Yousefbeiki, Juan R. Mosig, Andreas Peter Burg:
Near-Field Perturbation Effect on Constellation Error in Beam-Space MIMO. CoRR abs/1608.00606 (2016) - [i18]Mohsen Yousefbeiki, Andrew Charles Mallory Austin, Juan R. Mosig, Andreas Burg, Julien Perruisseau-Carrier:
Spatial Multiplexing of QPSK Signals with a Single Radio: Antenna Design and Over-the-Air Experiments. CoRR abs/1608.08644 (2016) - [i17]Orion Afisiadis, Andrew Charles Mallory Austin, Alexios Balatsoukas-Stimming, Andreas Peter Burg:
Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency. CoRR abs/1609.01139 (2016) - 2015
- [j24]Alexios Balatsoukas-Stimming, Andrew Charles Mallory Austin, Pavle Belanovic, Andreas Burg:
Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression. EURASIP J. Wirel. Commun. Netw. 2015: 142 (2015) - [j23]Harald Kröll, Stefan Zwicky, Benjamin Weber, Christoph Roth, David Tschopp, Christian Benkeser, Andreas Peter Burg, Qiuting Huang:
An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity. IEEE J. Solid State Circuits 50(7): 1690-1701 (2015) - [j22]Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. 14(2): 33:1-33:23 (2015) - [j21]Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Peter Burg:
LLR-Based Successive Cancellation List Decoding of Polar Codes. IEEE Trans. Signal Process. 63(19): 5165-5179 (2015) - [c99]Nicholas Preyss, Sara Rodriguez Egea, Andreas Burg:
Energy-proportional single-carrier frequency domain equalization for mmWave wireless communication. ACSSC 2015: 1133-1137 - [c98]Michael Meidlinger, Alexios Balatsoukas-Stimming, Andreas Burg, Gerald Matz:
Quantized message passing for LDPC codes. ACSSC 2015: 1606-1610 - [c97]Jiandong Mu, Aida Vosoughi, João Andrade, Alexios Balatsoukas-Stimming, Georgios Karakonstantis, Andreas Burg, Gabriel Falcão, Vítor Manuel Mendes da Silva, Joseph R. Cavallaro:
The impact of faulty memory bit cells on the decoding of spatially-coupled LDPC codes. ACSSC 2015: 1627-1631 - [c96]Adam Teman, Davide Rossi, Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg:
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. ASP-DAC 2015: 81-86 - [c95]Nicholas Preyss, Christian Senning, Andreas Burg, Wei-Chang Liu, Chun-Yi Liu, Shyh-Jye Jou:
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. A-SSCC 2015: 1-4 - [c94]Shrikanth Ganapathy, Georgios Karakonstantis, Adam Teman, Andreas Burg:
Mitigating the impact of faults in unreliable memories for error-resilient applications. DAC 2015: 102:1-102:6 - [c93]Jeremy Constantin, Lai Wang, Georgios Karakonstantis, Anupam Chattopadhyay, Andreas Burg:
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment. DATE 2015: 381-386 - [c92]Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg:
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. DATE 2015: 489-494 - [c91]Charalampos Antoniadis, Georgios Karakonstantis, Nestor E. Evmorfopoulos, Andreas Peter Burg, George I. Stamoulis:
On the statistical memory architecture exploration and optimization. DATE 2015: 543-548 - [c90]Hazar Yueksel, Lukas Kull, Andreas Burg, Matthias Braendli, Peter Buchmann, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Danny Luu, Thomas Toifl:
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. ESSCIRC 2015: 148-151 - [c89]Johannes Wüthrich, Alexios Balatsoukas-Stimming, Andreas Burg:
An FPGA-based accelerator for rapid simulation of SC decoding of polar codes. ICECS 2015: 633-636 - [c88]Nicholas Preyss, Andreas Burg:
Digital synchronization for symbol-spaced IEEE802.11ad Gigabit mmWave systems. ICECS 2015: 637-640 - [c87]Pascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg:
Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. ISCAS 2015: 1426-1429 - [c86]Andrea Bonetti, Adam Teman, Andreas Burg:
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. ISCAS 2015: 1850-1853 - [c85]Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Burg:
On metric sorting for successive cancellation list decoding of polar codes. ISCAS 2015: 1993-1996 - [c84]Andrew Charles Mallory Austin, Orion Afisiadis, Alexios Balatsoukas-Stimming, Andreas Peter Burg:
Demo: Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation. MobiHoc 2015: 407-408 - [c83]Nicholas Preyss, Lorenz Koestler, Andreas Burg:
Fractionally spaced complex sub-nyquist sampling for multi-gigabit 60 GHz wireless communication. MWSCAS 2015: 1-4 - [c82]Shrikanth Ganapathy, Adam Teman, Robert Giterman, Andreas Burg, Georgios Karakonstantis:
Approximate computing with unreliable dynamic memories. NEWCAS 2015: 1-4 - [c81]Alexios Balatsoukas-Stimming, Michael Meidlinger, Reza Ghanaatian, Gerald Matz, Andreas Burg:
A fully-unrolled LDPC decoder based on quantized message passing. SiPS 2015: 1-6 - [c80]Harald Kröll, Stefan Altorfer, Thomas Willi, Andreas Burg, Qiuting Huang:
Channel shortening and equalization based on information rate maximization for evolved GSM/EDGE. SiPS 2015: 1-6 - [i16]Christian Senning, Georgios Karakonstantis, Andreas Burg:
Cross-layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems. CoRR abs/1504.00234 (2015) - [i15]Alexios Balatsoukas-Stimming, Andreas Burg:
Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel. CoRR abs/1505.05404 (2015) - [i14]Alexios Balatsoukas-Stimming, Michael Meidlinger, Reza Ghanaatian, Gerald Matz, Andreas Peter Burg:
A Fully-Unrolled LDPC Decoder Based on Quantized Message Passing. CoRR abs/1510.04589 (2015) - [i13]Michael Meidlinger, Alexios Balatsoukas-Stimming, Andreas Peter Burg, Gerald Matz:
Quantized Message Passing for LDPC Codes. CoRR abs/1512.00210 (2015) - 2014
- [j20]Dimitrios S. Nikolopoulos, Hans Vandierendonck, Nikolaos Bellas, Christos D. Antonopoulos, Spyros Lalis, Georgios Karakonstantis, Andreas Burg, Uwe Naumann:
Energy Efficiency through Significance-Based Computing. Computer 47(7): 82-85 (2014) - [j19]Alexios Balatsoukas-Stimming, Andreas Burg:
Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage. IEEE Commun. Lett. 18(5): 849-852 (2014) - [j18]Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg:
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. IEEE Trans. Circuits Syst. II Express Briefs 61-II(4): 259-263 (2014) - [j17]Christian Senning, Lukas Bruderer, Josua Hunziker, Andreas Burg:
A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1860-1871 (2014) - [j16]Alexios Balatsoukas-Stimming, Alexandre J. Raymond, Warren J. Gross, Andreas Burg:
Hardware Architecture for List Successive Cancellation Decoding of Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 609-613 (2014) - [j15]Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg, Giovanni De Micheli:
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3155-3164 (2014) - [c79]João Andrade, Aida Vosoughi, Guohui Wang, Georgios Karakonstantis, Andreas Burg, Gabriel Falcão, Vítor Manuel Mendes da Silva, Joseph R. Cavallaro:
On the performance of LDPC and turbo decoder architectures with unreliable memories. ACSSC 2014: 542-547 - [c78]Christoph Roth, Christoph Studer, Georgios Karakonstantis, Andreas Burg:
Statistical data correction for unreliable memories. ACSSC 2014: 1890-1894 - [c77]Orion Afisiadis, Alexios Balatsoukas-Stimming, Andreas Burg:
A low-complexity improved successive cancellation decoder for polar codes. ACSSC 2014: 2116-2120 - [c76]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Andreas Burg, Giovanni De Micheli:
Data compression via logic synthesis. ASP-DAC 2014: 628-633 - [c75]Georgios Karakonstantis, Aviinaash Sankaranarayanan, Mohamed M. Sabry, David Atienza, Andreas Burg:
A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability. DATE 2014: 1-6 - [c74]Harald Kroll, Stefan Zwicky, Benjamin Weber, Christoph Roth, Christian Benkeser, Andreas Peter Burg, Qiuting Huang:
An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity. ESSCIRC 2014: 203-206 - [c73]Rubén Braojos, Ivan Beretta, Jeremy Constantin, Andreas Peter Burg, David Atienza:
A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead. EUC 2014: 265-272 - [c72]Junyi Liu, Helfried Peyrl, Andreas Burg, George A. Constantinides:
FPGA implementation of an interior point method for high-speed model predictive control. FPL 2014: 1-8 - [c71]Georg Kail, Patrick Maechler, Nicholas Preyss, Andreas Burg:
Robust asynchronous indoor localization using LED lighting. ICASSP 2014: 1866-1870 - [c70]Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Burg:
LLR-based successive cancellation list decoding of polar codes. ICASSP 2014: 3903-3907 - [c69]Christian Senning, Mikel Mendicute, Andreas Burg:
Cross layer energy-efficiency optimization for cognitive radio transceivers. ICASSP 2014: 3928-3932 - [c68]Konstantinos Alexandris, Alexios Balatsoukas-Stimming, Andreas Burg:
Measurement-based characterization of residual self-interference on a full-duplex MIMO testbed. SAM 2014: 329-332 - [c67]Harald Kroll, Stefan Zwicky, Reto Odermatt, Lukas Bruderer, Andreas Burg, Qiuting Huang:
A signal processor for Gaussian message passing. ISCAS 2014: 1969-1972 - [c66]Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Andreas Burg, Alexander Fish:
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. ISCAS 2014: 2177-2180 - [c65]Alexios Balatsoukas-Stimming, Georgios Karakonstantis, Andreas Burg:
Enabling complexity-performance trade-offs for successive cancellation decoding of polar codes. ISIT 2014: 2977-2981 - [c64]Alexios Balatsoukas-Stimming, Andreas Burg:
Faulty successive cancellation decoding of polar codes for the binary erasure channel. ISITA 2014: 448-452 - [c63]Matthew Weiner, Milovan Blagojevic, Sergey Skotnikov, Andreas Burg, Philippe Flatresse, Borivoje Nikolic:
27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI. ISSCC 2014: 464-465 - [i12]Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Burg:
LLR-based Successive Cancellation List Decoding of Polar Codes. CoRR abs/1401.3753 (2014) - [i11]Alexios Balatsoukas-Stimming, Andreas Burg:
Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage. CoRR abs/1404.1601 (2014) - [i10]Alexios Balatsoukas-Stimming, Andreas Burg:
Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel. CoRR abs/1404.1736 (2014) - [i9]Harald Kröll, Stefan Zwicky, Reto Odermatt, Lukas Bruderer, Andreas Burg, Qiuting Huang:
A Signal Processor for Gaussian Message Passing. CoRR abs/1404.3162 (2014) - [i8]Alexios Balatsoukas-Stimming, Mani Bastani Parizi, Andreas Peter Burg:
On Metric Sorting for Successive Cancellation List Decoding of Polar Codes. CoRR abs/1410.4460 (2014) - [i7]Alexios Balatsoukas-Stimming, Andrew Charles Mallory Austin, Pavle Belanovic, Andreas Burg:
Baseband and RF Hardware Impairments in Full-Duplex Wireless Systems: Experimental Characterisation and Suppression. CoRR abs/1412.4542 (2014) - [i6]Orion Afisiadis, Alexios Balatsoukas-Stimming, Andreas Peter Burg:
A Low-Complexity Improved Successive Cancellation Decoder for Polar Codes. CoRR abs/1412.5501 (2014) - 2013
- [c62]Andreas Winkelbauer, Gerald Matz, Andreas Burg:
Channel-optimized vector quantization with mutual information as fidelity criterion. ACSSC 2013: 851-855 - [c61]Alexios Balatsoukas-Stimming, Pavle Belanovic, Konstantinos Alexandris, Andreas Burg:
On self-interference suppression methods for low-complexity full-duplex MIMO. ACSSC 2013: 992-997 - [c60]Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici:
FireBird: PowerPC e200 based SoC for high temperature operation. CICC 2013: 1-4 - [c59]Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza:
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. DATE 2013: 396-399 - [c58]Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis:
Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE 2013: 503-508 - [c57]Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues:
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. ESSCIRC 2013: 197-200 - [c56]Stefan Zwicky, Christian Benkeser, Andreas Burg, Qiuting Huang:
Efficient vlsi implementation of reduced-state sequence estimation for wireless communications. ICASSP 2013: 2528-2532 - [c55]Pavle Belanovic, Alexios Balatsoukas-Stimming, Andreas Burg:
A multipurpose testbed for full-duplex wireless communications. ICECS 2013: 70-71 - [c54]Christian Senning, Andreas Burg:
Block-floating-point enhanced MMSE filter matrix computation for MIMO-OFDM communication systems. ICECS 2013: 787-790 - [c53]David E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer:
Live demonstration: Real-time audio restoration using sparse signal recovery. ISCAS 2013: 659 - [c52]Alexios Balatsoukas-Stimming, Nicholas Preyss, Alessandro Cevrero, Andreas Burg, Christoph Roth:
A parallelized layered QC-LDPC decoder for IEEE 802.11ad. NEWCAS 2013: 1-4 - [c51]Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli:
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. NEWCAS 2013: 1-4 - [e2]Andreas Burg, Ayse K. Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis:
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers. IFIP Advances in Information and Communication Technology 418, Springer 2013, ISBN 978-3-642-45072-3 [contents] - [i5]Alexios Balatsoukas-Stimming, Andreas Burg:
Tree Search Architecture for List SC Decoding of Polar Codes. CoRR abs/1303.7127 (2013) - [i4]Alexios Balatsoukas-Stimming, Georgios Karakonstantis, Andreas Burg:
Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes. CoRR abs/1307.5095 (2013) - 2012
- [j14]Patrick Maechler, Christoph Studer, David E. Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard G. Baraniuk:
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(3): 579-590 (2012) - [j13]Ahmed Yasir Dogan, Jeremy Constantin, David Atienza, Andreas Burg, Luca Benini:
Low-power processor architecture exploration for online biomedical signal analysis. IET Circuits Devices Syst. 6(5): 279-286 (2012) - [j12]Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus H. Gross:
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications. IEEE Trans. Circuits Syst. Video Technol. 22(11): 1577-1589 (2012) - [c50]Andreas Burg:
Session MP8a1: MIMO communications and signal processing I. ACSCC 2012: 451-452 - [c49]Maitane Barrenechea, Andreas Burg, Mikel Mendicute:
Low-complexity vector precoding for multi-user systems. ACSCC 2012: 453-457 - [c48]Christoph Roth, Christian Benkeser, Christoph Studer, Georgios Karakonstantis, Andreas Burg:
Data mapping for unreliable memories. Allerton Conference 2012: 679-685 - [c47]Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. ASAP 2012: 117-124 - [c46]Mohamed M. Sabry, Georgios Karakonstantis, David Atienza, Andreas Burg:
Design of energy efficient and dependable health monitoring systems under unreliable nanometer technologies. BODYNETS 2012: 52-58 - [c45]Georgios Karakonstantis, Christoph Roth, Christian Benkeser, Andreas Burg:
On the exploitation of the inherent error resilience of wireless systems under unreliable silicon. DAC 2012: 510-515 - [c44]Patrick Maechler, David E. Bellasi, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer:
Sparsity-based real-time audio restoration. DASIP 2012: 1-2 - [c43]Nicholas Preyss, Andreas Burg, Christoph Studer:
Layered detection and decoding in MIMO wireless systems. DASIP 2012: 1-8 - [c42]Ahmed Yasir Dogan, Jeremy Constantin, Martino Ruggiero, Andreas Burg, David Atienza:
Multi-core architecture design for ultra-low-power wearable health monitoring systems. DATE 2012: 988-993 - [c41]Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Burg:
A 2.78 mm2 65 nm CMOS gigabit MIMO iterative detection and decoding receiver. ESSCIRC 2012: 65-68 - [c40]Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. ESSCIRC 2012: 321-324 - [c39]Gabriel Falcão, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. FCCM 2012: 224-231 - [c38]Harald Kroll, Stefan Zwicky, Christian Benkeser, Qiuting Huang, Andreas Burg:
Low-complexity frequency synchronization for GSM systems: Algorithms and implementation. ICUMT 2012: 168-173 - [c37]Patrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg:
Hardware-efficient random sampling of fourier-sparse signals. ISCAS 2012: 269-272 - [c36]Rashid Iqbal, Pascal Andreas Meinerzhagen, Andreas Peter Burg:
Two-port low-power gain-cell storage array: Voltage scaling and retention time. ISCAS 2012: 2469-2472 - [c35]Karim Badawi, Christian Benkeser, Christoph Roth, Qiuting Huang, Andreas Burg:
A novel constrained-Viterbi algorithm with linear equalization and grouping assistance. ISWCS 2012: 231-235 - [c34]Muhammad Umer Khalid, Pascal Meinerzhagen, Andreas Burg:
Replica bit-line technique for embedded multilevel gain-cell DRAM. NEWCAS 2012: 77-80 - [c33]Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg:
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. VLSI-SoC (Selected Papers) 2012: 88-106 - [c32]Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg:
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. VLSI-SoC 2012: 159-164 - [c31]Sandro Belfanti, Christian Benkeser, Karim Badawi, Qiuting Huang, Andreas Burg:
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture. VLSI-SoC 2012: 279-282 - [e1]Srinivas Katkoori, Matthew R. Guthaus, Ayse K. Coskun, Andreas Burg, Ricardo Reis:
20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012. IEEE 2012, ISBN 978-1-4673-2657-5 [contents] - [i3]Christoph Roth, Christian Benkeser, Christoph Studer, Georgios Karakonstantis, Andreas Burg:
Data Mapping for Unreliable Memories. CoRR abs/1212.4950 (2012) - [i2]Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. IACR Cryptol. ePrint Arch. 2012: 50 (2012) - 2011
- [j11]Pierre Greisen, Simon Heinzle, Markus H. Gross, Andreas Burg:
An FPGA-based processing pipeline for high-definition stereo video. EURASIP J. Image Video Process. 2011: 18 (2011) - [j10]Pascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 173-182 (2011) - [j9]Simon Heinzle, Pierre Greisen, David Gallup, Christine Chen, Daniel Saner, Aljoscha Smolic, Andreas Burg, Wojciech Matusik, Markus H. Gross:
Computational stereo camera system with programmable control loop. ACM Trans. Graph. 30(4): 94 (2011) - [c30]Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Peter Burg:
A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder. A-SSCC 2011: 297-300 - [c29]Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
Synthesis strategies for sub-VT systems. ECCTD 2011: 552-555 - [c28]Patrick Maechler, Norbert Felber, Andreas Peter Burg:
Random sampling ADC for sparse spectrum sensing. EUSIPCO 2011: 1200-1204 - [c27]Pascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg:
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. ACM Great Lakes Symposium on VLSI 2011: 343-346 - [c26]Christoph Roth, Alessandro Cevrero, Christoph Studer, Yusuf Leblebici, Andreas Burg:
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. ISCAS 2011: 1772-1775 - [c25]Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini:
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing. PATMOS 2011: 102-111 - 2010
- [j8]Pierre Greisen, Simon Haene, Andreas Burg:
Simulation and Emulation of MIMO Wireless Baseband Transceivers. EURASIP J. Wirel. Commun. Netw. 2010 (2010) - [c24]Patrick Maechler, Pierre Greisen, Norbert Felber, Andreas Burg:
Matching pursuit: Evaluation and implementatio for LTE channel estimation. ISCAS 2010: 589-592 - [c23]Lukas Bruderer, Christoph Studer, Markus Wenk, Dominik Seethaler, Andreas Burg:
VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection. ISCAS 2010: 3745-3748 - [c22]Christoph Studer, Markus Wenk, Andreas Burg:
VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems. VLSI-SoC (Selected Papers) 2010: 128-154 - [c21]Markus Wenk, Lukas Bruderer, Andreas Burg, Christoph Studer:
Area- and throughput-optimized VLSI architecture of sphere decoding. VLSI-SoC 2010: 189-194 - [c20]Christoph Studer, Markus Wenk, Andreas Burg:
MIMO transmission with residual transmit-RF impairments. WSA 2010: 189-196 - [i1]Christoph Studer, Markus Wenk, Andreas Burg:
MIMO Transmission with Residual Transmit-RF Impairments. CoRR abs/1002.0406 (2010)
2000 – 2009
- 2009
- [j7]Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang:
Design and Optimization of an HSDPA Turbo Decoder ASIC. IEEE J. Solid State Circuits 44(1): 98-106 (2009) - [j6]Stefan Eberli, Andreas Burg, Wolfgang Fichtner:
Implementation of a 2×2 MIMO-OFDM receiver on an application specific processor. Microelectron. J. 40(11): 1642-1649 (2009) - 2008
- [j5]Christoph Studer, Andreas Burg, Helmut Bölcskei:
Soft-output sphere decoding: algorithms and VLSI implementation. IEEE J. Sel. Areas Commun. 26(2): 290-300 (2008) - [j4]Simon Haene, David Perels, Andreas Burg:
A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization. IEEE J. Sel. Areas Commun. 26(6): 877-889 (2008) - [c19]Christoph Studer, Nicholas Preyss, Christoph Roth, Andreas Burg:
Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes. ACSCC 2008: 1137-1142 - [c18]Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang:
A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS. ISSCC 2008: 264-265 - 2007
- [c17]Gottfried Lechner, Andreas Burg:
Design of spatially multiplexed LDPC codes for multi-user detection. EUSIPCO 2007: 1304-1307 - [c16]C. Hess, Markus Wenk, Andreas Burg, Peter Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner:
Reduced-complexity mimo detector with close-to ml error rate performance. ACM Great Lakes Symposium on VLSI 2007: 200-203 - [c15]Andreas Burg, Dominik Seethaler, Gerald Matz:
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding. ISCAS 2007: 673-676 - [c14]Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner:
FFT Processor for OFDM Channel Estimation. ISCAS 2007: 1417-1420 - [c13]Peter Luethi, Andreas Burg, Simon Haene, David Perels, Norbert Felber, Wolfgang Fichtner:
VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition. ISCAS 2007: 1421-1424 - [c12]Andreas Burg, Simon Haene, Wolfgang Fichtner, Markus Rupp:
Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation. ISCAS 2007: 3530-3533 - 2006
- [c11]Andreas Burg, Moritz Borgmann, Markus Wenk, Christoph Studer, Helmut Bölcskei:
Advanced receiver algorithms for MIMO wireless communications. DATE 2006: 593-598 - [c10]Andreas Peter Burg, Markus Wenk, Wolfgang Fichtner:
VLSI implementation of pipelined sphere decoding with early termination. EUSIPCO 2006: 1-5 - [c9]David Perels, Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner:
A Frame-Start Detector for a 4×4 MIMO-OFDM System. ICASSP (4) 2006: 425-428 - [c8]Andreas Burg, Simon Haene, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner:
Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems. ISCAS 2006 - [c7]Simon Haene, Andreas Burg, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner:
Silicon implementation of an MMSE-based soft demapper for MIMO-BICM. ISCAS 2006 - [c6]Markus Wenk, Martin Zellweger, Andreas Burg, Norbert Felber, Wolfgang Fichtner:
K-best MIMO detection VLSI architectures achieving up to 424 Mbps. ISCAS 2006 - 2005
- [j3]Andreas Burg, Moritz Borgmann, Markus Wenk, Martin Zellweger, Wolfgang Fichtner, Helmut Bölcskei:
VLSI implementation of MIMO detection using the sphere decoding algorithm. IEEE J. Solid State Circuits 40(7): 1566-1577 (2005) - [c5]David Perels, Simon Haene, Peter Luethi, Andreas Peter Burg, Norbert Felber, Wolfgang Fichtner, Helmut Bölcskei:
ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs. ESSCIRC 2005: 215-218 - 2004
- [c4]Andreas Burg, Markus Wenk, Martin Zellweger, Marc Simon Wegmueller, Norbert Felber, Wolfgang Fichtner:
VLSI implementation of the sphere decoding algorithm. ESSCIRC 2004: 303-306 - [c3]Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin:
A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44 - 2003
- [j2]Ali Adjoudani, Eric C. Beck, Andreas Peter Burg, Goran M. Djuknic, Thomas G. Gvoth, David A. Haessig, Salim Manji, Michelle A. Milbrodt, Markus Rupp, Dragan Samardzija, Arnold B. Siegel, Tod Sizer, Cuong Tran, Susan Walker, Stephen A. Wilkus, Peter W. Wolniansky:
Prototype experience for MIMO BLAST over third-generation wireless system. IEEE J. Sel. Areas Commun. 21(3): 440-451 (2003) - [j1]Markus Rupp, Andreas Burg, Eric C. Beck:
Rapid prototyping for wireless designs: the five-ones approach. Signal Process. 83(7): 1427-1444 (2003) - [c2]Andreas Burg, Norbert Felber, Wolfgang Fichtner:
A 50 Mbps 4×4 maximum likelihood decoder for multiple-input multiple-output systems with QPSK modulation. ICECS 2003: 332-335 - [c1]Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner:
Variable delay ripple carry adder with carry chain interrupt detection. ISCAS (5) 2003: 113-116
Coauthor Index
[j68] [j65] [c171] [c170] [i43] [c168] [c166] [c164] [c162] [i42] [j62] [j61] [j60] [c158] [c157] [i41] [i39] [j58] [c155] [c150] [j51] [j46] [c149] [c148] [c147] [c146] [c145] [c144] [c139] [i34] [i33] [i31] [c137] [c136] [i30] [j37] [j36] [c124] [c122] [i29] [j34] [c120] [c116] [c115] [i26] [i25] [i24] [i23] [i22] [c114] [c104] [c101] [c100] [i20] [i17] [j24] [j21] [c98] [c97] [c89] [c85] [c84] [c81] [i15] [i14] [i13] [j19] [j16] [c77] [c70] [c68] [c65] [c64] [i12] [i11] [i10] [i8] [i7] [i6] [c61] [c55] [c52] [i5] [i4]
Pascal Andreas Meinerzhagen
aka: Pascal Meinerzhagen
aka: Pascal Meinerzhagen
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