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ORCIDTetsuo Hironaka
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2020 – today
- 2021
[j12]Tomoya Michinaka, Hideyuki Kawabata
, Tetsuo Hironaka:
Rumpfr: A Fast and Memory Leak-free Rust Binding to the GNU MPFR Library. J. Inf. Process. 29: 676-684 (2021)
2010 – 2019
- 2019
- [j11]Yushi Kondoh, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka:
Efficient Searching for Essential API Member Sets based on Inclusion Relation Extraction. Int. J. Networked Distributed Comput. 7(4): 149-157 (2019) - [j10]Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka:
SAIFU: Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code. Int. J. Networked Distributed Comput. 7(4): 167-174 (2019) - [j9]Yuya Kono, Hideyuki Kawabata, Tetsuo Hironaka:
Resolving Ambiguous Types in Haskell by Checking Uniqueness of Type Variable Assignments under Type Class Constraints. J. Inf. Process. 27: 87-94 (2019) - [j8]Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka:
Easy-going Development of Event-Driven Applications by Iterating a Search-Select-Superpose Loop. J. Inf. Process. 27: 257-267 (2019) - [c18]Masahiro Hata, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka:
OSAIFU: A Source Code Factorizer on Android Studio. ICSME 2019: 422-425 - [c17]Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka:
Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code. SERA 2019: 13-18 - [c16]Yushi Kondoh, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka:
Extracting Inclusion Graphs of API Member Sets to Improve Searchability. SERA 2019: 53-59 - 2018
- [c15]Hideyuki Kawabata, Yuta Tanaka, Mai Kimura, Tetsuo Hironaka:
Traf: A Graphical Proof Tree Viewer Cooperating with Coq Through Proof General. APLAS 2018: 157-165 - 2015
- [j7]Tetsuo Hironaka:
Foreword. IEICE Trans. Inf. Syst. 98-D(2): 219 (2015) - 2012
- [j6]Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro:
A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. IEICE Trans. Inf. Syst. 95-D(2): 324-334 (2012) - 2011
- [c14]Kazuya Tanigawa, Tetsuo Hironaka:
Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area. ISOCC 2011: 187-190 - [c13]Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro:
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. ReConFig 2011: 448-454 - 2010
- [c12]Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka:
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. ARC 2010: 388-393
2000 – 2009
- 2008
- [j5]Takahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo:
Evaluation of low-energy and high-performance processor using variable stages pipeline technique. IET Comput. Digit. Tech. 2(3): 230-238 (2008) - [c11]Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka:
Exploring compact design on high throughput coarse grained reconfigurable architectures. FPL 2008: 543-546 - [c10]Kazuya Tanigawa, Tetsuo Hironaka:
Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. FPT 2008: 273-276 - 2007
- [j4]Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka:
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. 90-C(11): 2157-2160 (2007) - 2006
- [j3]Takahiro Sasaki, Tetsuo Hironaka, Naoki Nishimura, Noriyoshi Yoshida:
Scheduling support hardware for multiprocessor system and its evaluations. Syst. Comput. Jpn. 37(2): 79-95 (2006) - [c9]Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa:
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300 - 2005
- [j2]Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide:
Chip size and performance evaluations of shared cache for on-chip multiprocessor. Syst. Comput. Jpn. 36(9): 1-13 (2005) - [c8]Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch:
Design of superscalar processor with multi-bank register file. ISCAS (4) 2005: 3507-3510 - 2004
- [c7]Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka:
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC 2004: 551-552 - 2003
- [c6]Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka:
A novel hierarchical multi-port cache. ESSCIRC 2003: 405-408 - [c5]Kazuya Tanigawa, Takashi Kawasaki, Tetsuo Hironaka:
A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism. FPT 2003: 311-314 - 2002
- [c4]Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida:
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. FPL 2002: 434-443 - 2000
- [j1]Takahiro Sasaki, Tetsuo Hironaka, Seiji Fujino:
Performance Improvements of Thakore's Algorithm with Speculative Execution Technique and Dynamic Task Scheduling. Informatica (Slovenia) 24(1) (2000) - [c3]Naoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka:
Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system. ASP-DAC 2000: 29-30
1990 – 1999
- 1993
- [c2]Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura:
A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing 1993: 308-317 - 1992
- [c1]Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki J. Murakami, Shinji Tomita:
Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. ICS 1992: 272-281
Coauthor Index
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