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ORCIDVassilis Paliouras
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- affiliation: University of Patras, Greece
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2020 – today
- 2024
[j22]Vasilis Sakellariou
, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis:
A Multiplier-Free RNS-Based CNN Accelerator Exploiting Bit-Level Sparsity. IEEE Trans. Emerg. Top. Comput. 12(2): 667-683 (2024)- [c123]Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis:
An end-to-end RNS CNN Accelerator. AICAS 2024: 75-79 - [c122]Francesco Regazzoni, Gergely Ács, Albert Zoltan Aszalos, Christos Avgerinos, Nikolaos Bakalos, Josep Lluis Berral, Joppe W. Bos, Marco Brohet, Andrés G. Castillo Sanz, Gareth T. Davies, Stefanos Florescu, Pierre-Elisée Flory, Alberto Gutierrez-Torre, Evangelos Haleplidis, Alice Héliou, Sotirios Ioannidis, Alexander Islam El-Kady, Katarzyna Kapusta, Konstantina Karagianni, Pieter Kruizinga, Kyrian Maat, Zoltán Ádám Mann, Kalliopi Mastoraki, SeoJeong Moon, Maja Nisevic, Balázs Pejó, Kostas Papagiannopoulos, Vassilis Paliouras, Paolo Palmieri, Francesca Palumbo, Juan Carlos Pérez Baun, Péter Pollner, Eduard Porta-Pardo, Luca Pulina, Muhammad Ali Siddiqi, Daniela Spajic, Christos Strydis, Georgios Tasopoulos, Vincent Thouvenot, Christos Tselios, Apostolos P. Fournaris:
SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data Space. DATE 2024: 1-4 - [c121]Thodoris Spanos, Fran Fabra, José A. Lopez-Salcedo, Gonzalo Seco-Granados, Nikos Kanistras, Ivan Lapin, Vassilis Paliouras:
Angle of Arrival Estimation Using SRS in 5G NR Uplink Scenarios. WIPHAL 2024 - 2023
- [j21]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Path-Based Delay Variation Models for Parallel-Prefix Adders. IEEE Trans. Emerg. Top. Comput. 11(3): 689-705 (2023) - [j20]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams. IEEE Trans. Emerg. Top. Comput. 11(4): 1002-1017 (2023) - [c120]Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis:
Modified Logarithmic Multiplication Approximation for Machine Learning. AICAS 2023: 1-5 - [c119]Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis:
A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity. ARITH 2023: 101 - [c118]Emmanouil Kavvousanos, Vasilis Sakellariou, Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis:
Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization. ARITH 2023: 102-109 - [c117]Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras:
Received Power Maximization with Practical Phase-Dependent Amplitude Response in RIS-Aided OFDM Wireless Communications. ICASSP 2023: 1-5 - [c116]Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras, George C. Alexandropoulos:
Secrecy Rate Maximization in RIS-Enabled OFDM Wireless Communications: The Circuit-Based Reflection Model Case. ICC Workshops 2023: 1529-1534 - [c115]Alexander El-Kady, Apostolos P. Fournaris, Vassilis Paliouras:
Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis. ICCAD 2023: 1-7 - [c114]Emmanouil Kavvousanos, Ioannis Kouretas, Vassilis Paliouras, Thanos Stouraitis:
A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights. ICECS 2023: 1-4 - 2022
- [c113]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees. ISCAS 2022: 924-928 - [c112]Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis:
A High-performance RNS LSTM block. ISCAS 2022: 1264-1268 - [c111]Emmanouil Kavvousanos, Vassilis Paliouras:
A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation. MOCAST 2022: 1-4 - [c110]Thodoris Spanos, Vassilis Paliouras:
Hardware Aspects of Iterative Receivers for V2X Applications. MOCAST 2022: 1-4 - [c109]Dimitris Vordonis, Dimitris Kompostiotis, Vassilis Paliouras:
Reconfigurable Intelligent Surface-Aided OFDM Wireless Communications: Hardware Aspects of Reflection Optimization Methods. MOCAST 2022: 1-4 - [c108]Alexander El-Kady, Apostolos P. Fournaris, Evangelos Haleplidis, Vassilis Paliouras:
High-Level Synthesis design approach for Number-Theoretic Multiplier. VLSI-SoC 2022: 1-6 - 2021
- [j19]Dimitris Vordonis, Vassilis Paliouras:
Hardware Implementation and Performance Analysis of Improved Sphere Decoder in Spatially Correlated Massive MIMO Channels. IEEE Open J. Commun. Soc. 2: 2680-2694 (2021) - [j18]Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
Sum Propagate Adders. IEEE Trans. Emerg. Top. Comput. 9(3): 1479-1488 (2021) - [j17]Ahmed Mahdi, Nikos Kanistras, Vassilis Paliouras:
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 51-64 (2021) - [c107]Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
Sum Propagate Adders. ARITH 2021: 110 - [c106]Emmanouil Kavvousanos, Vassilis Paliouras:
Optimizing Deep Learning Decoders for FPGA Implementation. FPL 2021: 271-272 - [c105]Dimitris Chytas, Vassilis Paliouras:
A 5G-code based iterative Non-Binary LDPC decoder. ICECS 2021: 1-6 - [c104]Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani H. Saleh, Thanos Stouraitis:
On Reducing the Number of Multiplications in RNS-based CNN Accelerators. ICECS 2021: 1-6 - [c103]Chris Andriakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
A Novel Stochastic Polar Architecture for All-Digital Transmission. ISCAS 2021: 1-5 - [c102]Ioannis Kouretas, Vassilis Paliouras:
Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference. ISCAS 2021: 1-5 - [c101]Vasilis Sakellariou, Vassilis Paliouras:
An FPGA Accelerator for Spiking Neural Network Simulation and Training. ISCAS 2021: 1-5 - [c100]Ioannis Kouretas, Vassilis Paliouras:
Hardware Aspects of Parallel Neural Network Implementation. MOCAST 2021: 1-4 - [c99]Alexander El-Kady, Apostolos P. Fournaris, Thanasis Tsakoulis, Evangelos Haleplidis, Vassilis Paliouras:
High-Level Synthesis design approach for Number-Theoretic Transform Implementations. VLSI-SoC 2021: 1-6 - 2020
- [j16]Mark G. Arnold, Vassilis Paliouras, Ioannis Kouretas:
Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation. IEEE Trans. Computers 69(12): 1719-1732 (2020) - [c98]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations. ARITH 2020: 88-95 - [c97]Emmanouil Kavvousanos, Vassilis Paliouras:
An Iterative Approach to Syndrome-based Deep Learning Decoding. GLOBECOM (Workshops) 2020: 1-6 - [c96]Dimitris Chytas, Vassilis Paliouras:
Approximate Sorting Check Node Processing in Non-Binary LDPC Decoders. ICECS 2020: 1-4 - [c95]Kleanthis Papachatzopoulos, Chris Andriakopoulos, Vassilis Paliouras:
Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j15]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2546-2559 (2019) - [c94]Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, John R. Cowles:
Under- and Overflow Detection in the Residue Logarithmic Number System. ARITH 2019: 112-115 - [c93]Konstantina Karagianni, Vassilis Paliouras:
Versatile Hardware Generation of alpha-Stable Noise for PLC Channel Emulation. ICECS 2019: 646-649 - [c92]Ioannis Kouretas, Vassilis Paliouras:
Simplified Hardware Implementation of the Softmax Activation Function. MOCAST 2019: 1-4 - [c91]Emmanouil Kavvousanos, Vassilis Paliouras:
Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes. NORCAS 2019: 1-6 - [c90]Dimitris Vordonis, Vassilis Paliouras:
Sphere Decoder for Massive MIMO Systems. NORCAS 2019: 1-6 - [c89]Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, Austin Morgan:
One-Hot Residue Logarithmic Number Systems. PATMOS 2019: 97-102 - [c88]Ioannis Kouretas, Vassilis Paliouras:
Radix-3 low-complexity modulo-M multipliers. PATMOS 2019: 107-112 - 2018
- [j14]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 572-576 (2018) - [j13]Panagiotis Sakellariou, Vassilis Paliouras:
Reconfigurable RO-Path Delay Sensor. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 2027-2031 (2018) - [j12]Ioannis Tsatsaragkos, Vassilis Paliouras:
A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 182-195 (2018) - [c87]Ioannis Kouretas, Vassilis Paliouras:
Hardware aspects of Long Short Term Memory. ICECS 2018: 525-528 - [c86]Emmanouil Kavvousanos, Vassilis Paliouras, Ioannis Kouretas:
Simplified Deep-Learning-based decoders for linear block codes. ICECS 2018: 769-772 - [c85]Christos Andriakopoulos, Vassilis Paliouras:
Data representation and hardware aspects in a fully-folded successive-cancellation polar decoder. MOCAST 2018: 1-4 - [c84]Andreas Kalampoukas, Vassilis Paliouras:
A novel algorithm and hardware architecture for low-complexity soft demappers. MOCAST 2018: 1-4 - [c83]Ioannis Kouretas, Vassilis Paliouras:
Logarithmic number system for deep learning. MOCAST 2018: 1-4 - [c82]Vassilis Paliouras, Konstantina Karagianni, Yann Oster:
Low-cost soft-error compensation for transposed FIR digital filters. MOCAST 2018: 1-4 - [c81]Vassilis Paliouras, Konstantina Karagianni, Yann Oster:
Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines. PATMOS 2018: 183-190 - 2017
- [c80]Nikolaos M. Avouris, Kyriakos N. Sgarbas, Vassilis Paliouras, Michalis Koukias:
Work in progress: An introduction to computing course using a Python-based experiential approach. EDUCON 2017: 1663-1666 - [c79]Georgios Perris-Samios, Vassilis Paliouras:
An approximate hardware check node for λ-min-based LDPC decoders. EUSIPCO 2017: 1354-1357 - [c78]Giorgos Tsiaras, Vassilis Paliouras:
Logarithmic number system addition-subtraction using fractional normalization. ISCAS 2017: 1-4 - [c77]Alexios Thanos, Vassilis Paliouras:
Hardware trade-offs for massive MIMO uplink detection based on Newton iteration method. MOCAST 2017: 1-4 - [c76]Giorgos Tsiaras, Vassilis Paliouras:
Multi-operand logarithmic addition/subtraction based on Fractional Normalization. MOCAST 2017: 1-4 - 2016
- [j11]Panagiotis Sakellariou, Vassilis Paliouras:
Application-Specific Low-Power Multipliers. IEEE Trans. Computers 65(10): 2973-2985 (2016) - [c75]Kleanthis Papachatzopoulos, Ioannis Kouretas, Vassilis Paliouras:
Dynamic delay variation behaviour of RNS multiply-add architectures. ISCAS 2016: 1978-1981 - 2015
- [j10]Ioannis Tsatsaragkos, Vassilis Paliouras:
Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 766-770 (2015) - [j9]Ahmed Mahdi, Vassilis Paliouras:
On the Encoding Complexity of Quasi-Cyclic LDPC Codes. IEEE Trans. Signal Process. 63(22): 6096-6108 (2015) - 2014
- [j8]Ahmed Mahdi, Vassilis Paliouras:
A Low Complexity-High Throughput QC-LDPC Encoder. IEEE Trans. Signal Process. 62(10): 2696-2708 (2014) - [c74]P. Mermigkas, Vassilis Paliouras:
Effective sum of squares implementation for BPSK soft-decision decoding. ICECS 2014: 822-825 - [c73]Christos Vasilopoulos, Vassilis Paliouras:
A technique for the identification of trapping sets in LDPC codes. ICECS 2014: 838-841 - 2013
- [j7]Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras:
Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters. IEEE Trans. Computers 62(11): 2196-2209 (2013) - [c72]Ioannis Kouretas, Vassilis Paliouras:
Delay-variation-tolerant FIR filter architectures based on the Residue Number System. ISCAS 2013: 2223-2226 - [c71]Nikos Kanistras, Vassilis Paliouras:
A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm. SiPS 2013: 89-94 - 2012
- [c70]Ahmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras:
Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. ICECS 2012: 89-92 - [c69]Panagiotis Sakellariou, Vassilis Paliouras:
Low-power two's-complement multiplication based on selective activation. ICECS 2012: 452-455 - [c68]Ioannis Kouretas, Vassilis Paliouras:
Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation. ISCAS 2012: 1231-1234 - [c67]Panagiotis Sakellariou, Vassilis Paliouras:
Low-Power Delay Sensors on FPGAs. PATMOS 2012: 194-204 - [c66]Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikos Kanistras, Ahmed Mahdi, Vassilis Paliouras:
An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems. ICSAMOS 2012: 286-293 - [c65]Ahmed Mahdi, Vassilis Paliouras:
Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders. SiPS 2012: 1-6 - [c64]G. Spourlis, Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras:
Error Floor Compensation for LDPC Codes Using Concatenated Schemes. SiPS 2012: 155-160 - [c63]Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras:
Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding. SiPS 2012: 276-281 - 2011
- [j6]Nikos Kanistras, Vassilis Paliouras:
Impact of Approximation Error on the Decisions of LDPC Decoding. J. Signal Process. Syst. 64(1): 41-59 (2011) - [c62]Mark G. Arnold, John R. Cowles, Vassilis Paliouras, Ioannis Kouretas:
Towards a Quaternion Complex Logarithmic Number System. IEEE Symposium on Computer Arithmetic 2011: 33-42 - [c61]Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras:
A Residue Logarithmic Number System ALU using interpolation and cotransformation. ASAP 2011: 255-258 - [c60]Ioannis Paraskevakos, Vassilis Paliouras:
A flexible high-throughput hardware architecture for a gaussian noise generator. ICASSP 2011: 1673-1676 - [c59]Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras:
A syndrome-based LDPC decoder with very low error floor. DSP 2011: 1-6 - [c58]Ioannis Tsatsaragkos, Nikos Kanistras, Vassilis Paliouras:
Multiple LDPC decoder of very low bit-error rate. DSP 2011: 1-6 - [c57]E. Theodorakis, Vassilis Paliouras:
On the impact of encoding on the complexity of residue arithmetic circuits. ICECS 2011: 149-152 - [c56]Rodoula Makri, Petros Tsenes, Dimitrios Economou, Yannis Papananos, Dimitrios Dervenis, Michael K. Birbas, John C. Kikidis, Vassilis Paliouras, Grigorios Kalivas, Alexios N. Birbas, Panos Karaivazoglou, Yorgos Stratakos, John Korinthios, Stelios Siskos, Alkis A. Hatzopoulos, John Komninos, Serafeim Katsikas, Konstantinos N. Voudouris, Andreas Rigas, George Agapiou, Polivios Raxis:
Next generation millimeter wave backhaul radio: Overall system design for GbE 60GHz PtP wireless radio of high CMOS integration. ICECS 2011: 338-341 - [c55]Nikos Kanistras, Ioannis Tsatsaragkos, Ahmed Mahdi, Konstantina Karagianni, Vassilis Paliouras, Fotios Gioulekas, E. Lalos, Kostas Adaos, Michael K. Birbas, Panos Karaivazoglou, M. V. Koziotis, M. Perakis:
Digital baseband challenges for a 60GHz gigabit link. ICECS 2011: 346-349 - [c54]Ioannis Tsatsaragkos, Vassilis Paliouras:
A flexible layered LDPC decoder. ISWCS 2011: 36-40 - [c53]Andreas Brokalakis, Vassilis Paliouras:
Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems. SiPS 2011: 7-12 - [c52]Ahmed Mahdi, Nikos Kanistras, Vassilis Paliouras:
An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes. SiPS 2011: 328-333 - 2010
- [c51]Ioannis Kouretas, Vassilis Paliouras:
RNS multi-voltage low-power multiply-add unit. ICECS 2010: 9-12 - [c50]Angelos Spanos, Vassilis Paliouras:
VLSI implementation and performance of turbo decoding stopping criteria. ICECS 2010: 470-474 - [c49]Ioannis Kouretas, Vassilis Paliouras:
Residue arithmetic bases for reducing delay variation. ISCAS 2010: 3885-3888 - [c48]Ioannis Kouretas, Vassilis Paliouras:
Residue Arithmetic for Designing Low-Power Multiply-Add Units. PATMOS 2010: 31-40
2000 – 2009
- 2009
- [j5]Ioannis Kouretas, Vassilis Paliouras:
A Low-Complexity High-Radix RNS Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(11): 2449-2462 (2009) - [j4]Theodoros Giannopoulos, Vassilis Paliouras:
A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. J. Signal Process. Syst. 56(2-3): 141-153 (2009) - [c47]Ioannis Kouretas, Vassilis Paliouras:
Variation-tolerant Design Using Residue Number System. DSD 2009: 157-163 - [c46]Ioannis Kouretas, Vassilis Paliouras:
High-radix residue arithmetic bases for low-power DSP systems. DPS 2009: 1-6 - [c45]Ioannis Kouretas, Vassilis Paliouras:
Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units. PATMOS 2009: 26-35 - 2008
- [c44]Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras:
Low-power logarithmic number system addition/subtraction and their impact on digital filters. ISCAS 2008: 692-695 - [c43]Eleni Fotopoulou, Vassilis Paliouras, Thanos Stouraitis:
A frequency-domain interpolation implementation for OFDM transmitters. ISWPC 2008: 628-632 - [c42]Theodoros Giannopoulos, Vassilis Paliouras:
Relationship among BER, power consumption and PAPR. ISWPC 2008: 633-637 - [c41]Panos Karaivazoglou, Konstantina Karagianni, Vassilis Paliouras, Kostas Berberidis:
Roundoff error effects on a Quasi-Newton frequency domain channel equalizer. ISWPC 2008: 638-641 - [c40]G. Aggouras, Vassilis Paliouras:
On the implementation of bus-based architectures for LDPC decoding. ISWPC 2008: 642-645 - [c39]Nikos Kanistras, Vassilis Paliouras:
Impact of roundoff errors in LDPC decoding. ISWPC 2008: 646-650 - [c38]D. Pettas, Vassilis Paliouras:
Packet detector for multiband UWB. ISWPC 2008: 781-784 - [c37]Ioannis Kouretas, Vassilis Paliouras:
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication. PATMOS 2008: 93-102 - [c36]Nikos Kanistras, Vassilis Paliouras:
Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding. SiPS 2008: 100-105 - 2007
- [c35]Charalambos Basetas, Ioannis Kouretas, Vassilis Paliouras:
Low-Power Digital Filtering Based on the Logarithmic Number System. PATMOS 2007: 546-555 - [c34]Dimitris Gkrimpas, Vassilis Paliouras:
On The Complexity of Joint Demodulation and Convolutional Decoding. SiPS 2007: 669-674 - 2006
- [j3]Johan Vounckx, Vassilis Paliouras:
Editorial. J. Low Power Electron. 2(1) (2006) - [c33]Theodoros Giannopoulos, Vassilis Paliouras:
Novel efficient weighting factors for PTS-based PAPR reduction in low-power OFDM transmitters. EUSIPCO 2006: 1-5 - [c32]Theodoros Giannopoulos, Vassilis Paliouras:
A novel technique for low-power D/A conversion based on PAPR reduction. ISCAS 2006 - [c31]Theodoros Giannopoulos, Vassilis Paliouras:
Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters. PATMOS 2006: 203-213 - [c30]Konstantina Karagianni, Vassilis Paliouras, Theodoros Giannopoulos:
Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems. SiPS 2006: 200-204 - [c29]Spyros Gidaros, Vassilis Paliouras:
Simplified Criteria for Early Iterative Decoding Termination. SiPS 2006: 209-214 - [c28]Theodoros Giannopoulos, Vassilis Paliouras:
A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. SiPS 2006: 434-439 - 2005
- [c27]Panagiotis D. Vouzis, Mark G. Arnold, Vassilis Paliouras:
Using CLNS for FFTs in OFDM demodulation of UWB receivers. ISCAS (4) 2005: 3954-3957 - [c26]Theodoros Giannopoulos, Vassilis Paliouras:
Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction. PATMOS 2005: 177-186 - [c25]Konstantina Karagianni, Vassilis Paliouras:
Low-Power Aspects of Nonlinear Signal Processing. PATMOS 2005: 518-527 - [e2]Vassilis Paliouras, Johan Vounckx, Diederik Verkest:
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings. Lecture Notes in Computer Science 3728, Springer 2005, ISBN 3-540-29013-3 [contents] - 2004
- [j2]Giorgos Dimitrakopoulos, Vassilis Paliouras:
A novel architecture and a systematic graph-based optimization methodology for modulo multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(2): 354-370 (2004) - [c24]Eleni Fotopoulou, Vassilis Paliouras:
An efficient computational method and a VLSI architecture for digital filtering of CP-OFDM signals. GLOBECOM 2004: 2393-2397 - [c23]Theodoros Giannopoulos, Vassilis Paliouras:
An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering. ISCAS (4) 2004: 85-88 - [c22]Stamatis Krommydas, Vassilis Paliouras:
An efficient memory compression scheme for 8 k FFT in a DVB-T receiver and the corresponding error model. ISCAS (4) 2004: 89-92 - [c21]Panagiotis D. Vouzis, Vassilis Paliouras:
Optimal Logarithmic Representation in Terms of SNR Behavior. PATMOS 2004: 760-769 - [e1]Enrico Macii, Odysseas G. Koufopavlou, Vassilis Paliouras:
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings. Lecture Notes in Computer Science 3254, Springer 2004, ISBN 3-540-23095-5 [contents] - 2003
- [c20]Eleni Fotopoulou, Vassilis Paliouras, Thanos Stouraitis:
A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems. ISCAS (2) 2003: 125-128 - [c19]Ioannis Kouretas, Vassilis Paliouras:
High-radix redundant circuits for RNS modulo rn-1, rn, or rn+1. ISCAS (5) 2003: 229-232 - 2002
- [c18]Vassilis Paliouras, Alexander Skavantzos, Thanos Stouraitis:
Multi-voltage low power convolvers using the polynomial residue number system. ACM Great Lakes Symposium on VLSI 2002: 7-11 - [c17]Ioannis Kouretas, Vassilis Paliouras:
High-radix modulo rn - 1 multipliers and adders. ICECS 2002: 561-564 - 2001
- [j1]Konstantina Karagianni, Vassilis Paliouras, George Diamantakos, Thanos Stouraitis:
Operation-Saving VLSI Architectures for 3D Geometrical Transformations. IEEE Trans. Computers 50(6): 609-622 (2001) - [c16]Vassilis Paliouras, Thanos Stouraitis:
Low-Power Properties of the Logarithmic Number System. IEEE Symposium on Computer Arithmetic 2001: 229-236 - [c15]Vassilis Paliouras, J. Dagres, Panagiotis Tsakalides, Thanos Stouraitis:
VLSI architectures for blind equalization based on fractional-order statistics. ICECS 2001: 799-802 - [c14]Vassilis Paliouras, Thanos Stouraitis:
Signal activity and power consumption reduction using the logarithmic number system. ISCAS (2) 2001: 653-656 - 2000
- [c13]Vassilis Paliouras, Thanos Stouraitis:
High-radix residue number system forward and inverse converters. ICECS 2000: 858-861 - [c12]Vassilis Paliouras, Thanos Stouraitis:
Logarithmic Number System for Low-Power Arithmetic. PATMOS 2000: 285-294
1990 – 1999
- 1999
- [c11]Vassilis Paliouras, Thanos Stouraitis:
Novel high-radix residue number system multipliers and adders. ISCAS (1) 1999: 451-454 - 1998
- [c10]Vassilis Paliouras, J. Karagiannis, G. Aggouras, Thanos Stouraitis:
A very-long instruction word digital signal processor based on the logarithmic number system. ICECS 1998: 59-62 - [c9]Vassilis Paliouras, Konstantina Karagianni, Thanos Stouraitis:
A VLSI architecture for fast and accurate floating-point sine/cosine evaluation. ICECS 1998: 473-476 - 1997
- [c8]Vassilis Paliouras, Thanos Stouraitis:
Area-time performance of VLSI FIR filter architectures based on residue arithmetic. EUROMICRO 1997: 576-583 - [c7]Konstantina Karagianni, George Diamantakos, Vassilis Paliouras, Thanos Stouraitis:
An operation-saving VLSI geometry engine core. ICASSP 1997: 607-610 - 1996
- [c6]E. N. Malamas, Vassilis Paliouras, Thanos Stouraitis:
Efficient algorithms and VLSI architectures for trigonometric functions in the logarithmic number system based on the subtraction function. ICECS 1996: 964-967 - 1995
- [c5]I. Orginos, Vassilis Paliouras, Thanos Stouraitis:
A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation. ISCAS 1995: 1992-1995 - 1994
- [c4]Vassilis Paliouras, Thanos Stouraitis:
Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors. ISCAS 1994: 79-82 - 1993
- [c3]Dimitrios Soudris, Vassilis Paliouras, Thanos Stouraitis, Alexander Skavantzos, Constantinos E. Goutis:
Systematic design of full adder-based architectures for convolution. ICASSP (1) 1993: 389-392 - [c2]Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis:
Methodology for the Design of Signed-digit DSP Processors. ISCAS 1993: 1833-1836 - 1992
- [c1]Dimitrios Soudris, Vassilis Paliouras, Thanos Stouraitis:
Systematic development of architectures for multidimensional DSP using the residue number system. ICASSP 1992: 397-400
Coauthor Index
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