default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDManoj Sachdev
Person information
SPARQL queries 
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j60]Yugal Kishore Maheshwari
, Manoj Sachdev:
A power-efficient, single-phase, contention-free flip-flop with only three clock transistors. Microelectron. J. 152: 106390 (2024)- [j59]Sheida Gohardehi, Manoj Sachdev:
Low-Power Row Driver for Digitally Driven OLEDoS Microdisplay. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2774-2782 (2024) - 2023
- [j58]Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev:
Enhancing Strong PUF Security With Nonmonotonic Response Quantization. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 55-64 (2023) - [c93]Yugal Maheshwari, Manoj Sachdev:
VLFF - A Very Low-power Flip-flop with only Two Clock Transistors. SOCC 2023: 1-6 - 2022
- [j57]Kleber Stangherlin, Manoj Sachdev:
Design and Implementation of a Secure RISC-V Microprocessor. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1705-1715 (2022) - [d1]Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev:
Testchip Measured CRPs of NMQ strong PUF. IEEE DataPort, 2022
- [i4]Kleber Stangherlin, Manoj Sachdev:
Design and Implementation of a Secure RISC-V Microprocessor. CoRR abs/2205.05095 (2022) - [i3]Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev:
Enhancing Strong PUF Security with Non-monotonic Response Quantization. CoRR abs/2206.03440 (2022) - [i2]Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev:
Design Exploration and Security Assessment of PUF-on-PUF Implementations. CoRR abs/2206.11840 (2022) - [i1]Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev:
Secure and Lightweight Strong PUF Challenge Obfuscation with Keyed Non-linear FSR. CoRR abs/2207.11181 (2022) - 2021
- [j56]Qing Li, Czang-Ho Lee, Mohsen Asad, William S. Wong, Manoj Sachdev:
Energy-Efficient Full-Swing Logic Circuits With Unipolar TFTs on Flexible Substrates. IEEE J. Solid State Circuits 56(6): 1949-1958 (2021) - [j55]Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev:
Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3265-3278 (2021) - [c92]Yugal Maheshwari, Kleber Stangherlin, Derek Wright, Manoj Sachdev:
Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop. ICECS 2021: 1-4 - [c91]Kleber Hugo Stangherlin, Manoj Sachdev:
Reliable Strong PUF Enrollment and Operation with Temperature and Voltage Optimization. ISQED 2021: 529-534 - 2020
- [j54]Ata Khorami, Roghayeh Saeidi, Manoj Sachdev:
A low-power low-offset charge-sharing technique for double-tail comparators. Microelectron. J. 102: 104842 (2020) - [j53]Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev:
Monitoring Aging Defects in STT-MRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4645-4656 (2020) - [c90]Qing Li, Czang-Ho Lee, William S. Wong, Manoj Sachdev:
Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology. CICC 2020: 1-4 - [c89]Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev:
Accelerating STT-MRAM Ramp-up Characterization. NEWCAS 2020: 303-306
2010 – 2019
- 2019
- [j52]Ata Khorami, Roghayeh Saeidi, Manoj Sachdev, Mohammad Sharifkhani:
A low-power dynamic comparator for low-offset applications. Integr. 69: 23-30 (2019) - [j51]Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev:
Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2519-2532 (2019) - [j50]Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev:
A Parametric DFT Scheme for STT-MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1685-1696 (2019) - [c88]Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev, Mahesh V. Tripunitara:
Strengthening PUFs using Composition. ICCAD 2019: 1-8 - [c87]Manoj Sachdev:
Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test. SoCC 2019: 1-2 - [c86]Ata Khorami, Manoj Sachdev, Mohammad Sharifkhani:
A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications. SoCC 2019: 11-16 - 2018
- [j49]Morteza Nabavi, Manoj Sachdev:
A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology. IEEE J. Solid State Circuits 53(2): 656-667 (2018) - [c85]Dhruv Patel, Derek Wright, Manoj Sachdev:
Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm. ETS 2018: 1-6 - [c84]Mahdi Elghazali, Manoj Sachdev, Ajoy Opal:
An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology. ISQED 2018: 214-220 - 2016
- [c83]Jaspal Singh Shah, Manoj Sachdev:
Radiation hardened pulsed-latches in 65-nm CMOS. CCECE 2016: 1-4 - [c82]Mahdi Elghazali, Manoj Sachdev, Ajoy Opal:
A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology. ISVLSI 2016: 421-425 - 2015
- [j48]Adam Neale, Maarten Jonkman, Manoj Sachdev:
Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs. IEEE Trans. Circuits Syst. II Express Briefs 62-II(4): 387-391 (2015) - [c81]Adam Neale, Manoj Sachdev:
A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS. CICC 2015: 1-4 - [c80]Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev:
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). FPGA 2015: 266 - [c79]Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev:
Voltage-Boosted Synchronizers. ACM Great Lakes Symposium on VLSI 2015: 307-312 - [c78]Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet:
VLSI implementation of high-throughput, low-energy, configurable MIMO detector. ICCD 2015: 535-542 - [c77]Afshin Seraj, Mohammad Maymandi-Nejad, Parvin Bahmanyar, Manoj Sachdev:
A Linear Comparator-Based Fully Digital Delay Element. ISVLSI 2015: 652-655 - [c76]Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev:
Runtime slack-deficit detection for a low-voltage DCT circuit. MWSCAS 2015: 1-4 - 2014
- [j47]Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet:
A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 160-171 (2014) - [c75]Mahdi Elghazali, Manoj Sachdev, Ajoy Opal:
A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology. CICC 2014: 1-4 - [c74]Adam Neale, Manoj Sachdev:
A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC. CICC 2014: 1-4 - [c73]Manoj Sachdev, Tetsuya Iizuka:
Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. CICC 2014: 1 - [c72]Mahdi Elghazali, Manoj Sachdev, Ajoy Opal:
A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications. NEWCAS 2014: 472-475 - [c71]Tahseen Shakir, Manoj Sachdev:
A body-bias based current sense amplifier for high-speed low-power embedded SRAMs. SoCC 2014: 444-448 - 2013
- [j46]Jaspal Singh Shah, David Nairn, Manoj Sachdev:
An Energy-Efficient Offset-Cancelling Sense Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 60-II(8): 477-481 (2013) - [j45]Pierce Chuang, David Li, Manoj Sachdev:
Constant Delay Logic Style. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 554-565 (2013) - [j44]Tasreen Charania, Ajoy Opal, Manoj Sachdev:
Analysis and Design of On-Chip Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 648-658 (2013) - [c70]Maofeng Yang, Nikolas P. Papadopoulos, Czang-Ho Lee, William S. Wong, Manoj Sachdev:
A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays. CICC 2013: 1-4 - 2012
- [j43]Pierce Chuang, David Li, Manoj Sachdev:
A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator. IEEE Trans. Circuits Syst. II Express Briefs 59-II(2): 108-112 (2012) - [j42]David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Richard Wong:
Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1626-1634 (2012) - [c69]Pierce Chuang, David Li, Manoj Sachdev, Vincent C. Gaudet:
A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS. CICC 2012: 1-4 - [c68]Mike Li, Manoj Sachdev:
Power delivery: Droop, jitter, test and debug story (Tutorial). CICC 2012: 1 - [c67]Tahseen Shakir, Manoj Sachdev:
A word-line boost driver design for low operating voltage 6T-SRAMs. MWSCAS 2012: 33-36 - [c66]Tahseen Shakir, Manoj Sachdev:
A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs. SoCC 2012: 66-71 - [c65]Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev:
Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block. VLSI-SoC 2012: 201-206 - [c64]Jaspal Singh Shah, David Nairn, Manoj Sachdev:
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. VLSI-SoC 2012: 275-278 - 2011
- [j41]Muhammad Nummer, Manoj Sachdev:
Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths. J. Electron. Test. 27(1): 9-17 (2011) - [j40]Mohammad Sharifkhani, Ehsan Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev:
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 883-894 (2011) - [c63]Danny Teng-Hsiang Tsuei, Mohamed-Yahia Dabbagh, Manoj Sachdev:
Multiprocessor FPGA implementation of a 2D digital filter. CCECE 2011: 630-633 - [c62]Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev:
Analysis of power supply noise mitigation circuits. CCECE 2011: 1250-1255 - [c61]David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong:
Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. CICC 2011: 1-4 - [c60]David Li, Pierce Chuang, David Nairn, Manoj Sachdev:
Design and analysis of metastable-hardened flip-flops in sub-threshold region. ISLPED 2011: 157-162 - [c59]Adam Neale, Manoj Sachdev:
Digitally programmable SRAM timing for nano-scale technologies. ISQED 2011: 518-524 - [c58]David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev:
Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops. ISQED 2011: 583-590 - 2010
- [c57]David Li, Pierce Chuang, Manoj Sachdev:
Comparative analysis and study of metastability on high-performance flip-flops. ISQED 2010: 853-860
2000 – 2009
- 2009
- [j39]Mohammad Sharifkhani, Manoj Sachdev:
SRAM Cell Stability: A Dynamic Perspective. IEEE J. Solid State Circuits 44(2): 609-619 (2009) - [j38]Mohammad Sharifkhani, Manoj Sachdev:
An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS. IEEE J. Solid State Circuits 44(2): 620-630 (2009) - [j37]Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev:
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC. IEEE J. Solid State Circuits 44(9): 2543-2553 (2009) - [j36]Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev:
A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(3): 566-573 (2009) - [j35]Nitin Mohan, Manoj Sachdev:
Low-Leakage Storage Cells for Ternary Content Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 604-612 (2009) - [j34]Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev:
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1187-1195 (2009) - [c56]Manoj Sachdev, Hong-Ha Vuong:
ESD design challenges. CICC 2009 - [c55]Hossein Sarbishaei, Manoj Sachdev:
ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology. CICC 2009: 697-700 - [c54]Pierce Chuang, David Li, Manoj Sachdev:
Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic. ISCAS 2009: 3038-3041 - 2008
- [j33]David Rennie, Manoj Sachdev:
A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(3): 796-803 (2008) - [c53]Shah M. Jahinuzzaman, Tahseen Shakir, Sumanjit Lubana, Jaspal Singh Shah, Manoj Sachdev:
A multiword based high speed ECC scheme for low-voltage embedded SRAMS. ESSCIRC 2008: 226-229 - [c52]Hooman Farkhani, Mohammad Maymandi-Nejad, Manoj Sachdev:
A fully digital ADC using a new delay element with enhanced linearity. ISCAS 2008: 2406-2409 - [c51]Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev:
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. ISQED 2008: 207-212 - 2007
- [j32]Nitin Mohan, Manoj Sachdev:
Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs. IEEE J. Solid State Circuits 42(9): 2054-2060 (2007) - [j31]Mohammad Sharifkhani, Manoj Sachdev:
Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 196-205 (2007) - [j30]Mohamed Elgebaly, Manoj Sachdev:
Variation-Aware Adaptive Voltage Scaling System. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 560-571 (2007) - [c50]Hossein Sarbishaei, Oleg Semenov, Manoj Sachdev:
Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os. CICC 2007: 149-152 - [c49]Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev:
Dynamic Data Stability in Low-power SRAM Design. CICC 2007: 237-240 - [c48]David Rennie, Manoj Sachdev:
A Novel Tri-State Binary Phase Detector. ISCAS 2007: 185-188 - [c47]David Rennie, Manoj Sachdev:
Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits. ISQED 2007: 305-310 - 2006
- [b1]Arman Vassighi, Manoj Sachdev:
Thermal and Power Management of Integrated Circuits. Series on Integrated Circuits and Systems, Springer 2006, ISBN 978-0-387-25762-4, pp. 1-179 - [j29]Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh:
New JETTA Editors, 2006. J. Electron. Test. 22(1): 9-10 (2006) - [j28]Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez:
Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. IEEE J. Solid State Circuits 41(10): 2334-2343 (2006) - [j27]Oleg Semenov, Hossein Sarbishaei, Valery Axelrad, Manoj Sachdev:
Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices. Microelectron. J. 37(6): 526-533 (2006) - [j26]Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev:
Design techniques and test methodology for low-power TCAMs. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 573-586 (2006) - [j25]Mohammad Maymandi-Nejad, Manoj Sachdev:
DTMOS Technique for Low-Voltage Analog Circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1151-1156 (2006) - [c46]Mohammad Sharifkhani, Manoj Sachdev:
A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer. CICC 2006: 205-208 - [c45]Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev:
Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories. CICC 2006: 297-300 - [c44]Mohammad Sharifkhani, Manoj Sachdev:
A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization. ISCAS 2006 - [c43]Mohammad Sharifkhani, Manoj Sachdev:
A low power SRAM architecture based on segmented virtual grounding. ISLPED 2006: 256-261 - [c42]Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev:
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. MTDT 2006: 55-64 - [c41]Nitin Mohan, Wilson Fung, Manoj Sachdev:
Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory. SoCC 2006: 253-256 - [c40]Nitin Mohan, Manoj Sachdev:
Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM. SoCC 2006: 311-314 - 2005
- [j24]Mohammad Maymandi-Nejad, Manoj Sachdev:
A monotonic digitally controlled delay element. IEEE J. Solid State Circuits 40(11): 2212-2219 (2005) - [j23]Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. Microelectron. J. 36(9): 801-809 (2005) - [j22]Bhaskar Chatterjee, Manoj Sachdev:
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1296-1304 (2005) - [c39]Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane:
Programmable techniques for cell stability test and debug in embedded SRAMs. CICC 2005: 443-446 - [c38]Mohammad Maymandi-Nejad, Manoj Sachdev:
A 0.8V Delta-Sigma modulator using DTMOS technique. ISCAS (4) 2005: 3684-3687 - [c37]Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev:
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. ISQED 2005: 427-432 - [c36]Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev:
Word line pulsing technique for stability fault detection in SRAM cells. ITC 2005: 10 - 2004
- [j21]Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi:
DFT for Delay Fault Testing of High-Performance Digital Circuits. IEEE Des. Test Comput. 21(3): 248-258 (2004) - [j20]Stephen Docking, Manoj Sachdev:
An analytical equation for the oscillation frequency of high-frequency ring oscillators. IEEE J. Solid State Circuits 39(3): 533-537 (2004) - [j19]Oleg Semenov, Michael S. Obrecht, Manoj Sachdev:
Evaluation of STI degradation using temperature dependence of leakage current in parasitic STI MOSFET. Microelectron. Reliab. 44(9-11): 1751-1755 (2004) - [j18]Oleg Semenov, Hossein Sarbishaei, Valery Axelrad, Manoj Sachdev:
The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness. Microelectron. Reliab. 44(9-11): 1817-1822 (2004) - [j17]Farhad H. A. Asgari, Manoj Sachdev:
A low-power reduced swing global clocking methodology. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 538-545 (2004) - [j16]Mohammad Maymandi-Nejad, Manoj Sachdev:
Correction to "A Digitally Programmable Delay Element: Design and Analysis". IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1126 (2004) - [c35]Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De:
Design optimizations for microprocessors at low temperature. DAC 2004: 2-5 - [c34]Nitin Mohan, Manoj Sachdev:
Low power dual matchline ternary content addressable memory. ISCAS (2) 2004: 633-636 - [c33]Christine Kwong, Bhaskar Chatterjee, Manoj Sachdev:
Modeling and designing energy-delay optimized wide domino circuits. ISCAS (2) 2004: 921-924 - [c32]Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. ISLPED 2004: 248-251 - [c31]Mohamed Elgebaly, Manoj Sachdev:
Efficient adaptive voltage scaling system through on-chip critical path emulation. ISLPED 2004: 375-380 - [c30]Shahab Ardalan, Manoj Sachdev:
An Overview of Substrate Noise Reduction Techniques. ISQED 2004: 291-296 - [c29]Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. ISQED 2004: 415-420 - [c28]Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez:
AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. ITC 2004: 1006-1015 - [c27]Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi:
A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. ITC 2004: 1108-1117 - 2003
- [j15]Muhammad Nummer, Manoj Sachdev:
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers. J. Electron. Test. 19(3): 299-314 (2003) - [j14]Oleg Semenov, Arman Vassighi, Manoj Sachdev:
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing. J. Electron. Test. 19(3): 341-352 (2003) - [j13]Muhammad Nummer, Manoj Sachdev:
Testing high-performance pipelined circuits with slow-speed testers. ACM Trans. Design Autom. Electr. Syst. 8(4): 506-521 (2003) - [j12]Mohammad Maymandi-Nejad, Manoj Sachdev:
A digitally programmable delay element: design and analysis. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 871-878 (2003) - [c26]Muhammad Nummer, Manoj Sachdev:
DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. DATE 2003: 10212-10217 - [c25]Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi:
Thermal Management of High Performance Microprocessors. DFT 2003: 313-319 - [c24]Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED 2003: 122-127 - [c23]Derek Wright, Manoj Sachdev:
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. ITC 2003: 39-47 - [c22]Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins:
Burn-in Temperature Projections for Deep Sub-micron Technologies. ITC 2003: 95-104 - 2002
- [j11]Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Des. Test Comput. 19(5): 36-43 (2002) - [j10]Wai Chung, Timothy Lo, Manoj Sachdev:
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 913-918 (2002) - [c21]Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi:
Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI. DFT 2002: 12-19 - [c20]Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi:
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. ITC 2002: 1130-1139 - [c19]Manoj Sachdev:
Multi-Gigahertz Digital Test Challenges and Techniques. ITC 2002: 1231 - [c18]Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta:
Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 16-17 - 2001
- [j9]Manoj Sachdev:
Current-Based Testing for Deep-Submicron VLSIs. IEEE Des. Test Comput. 18(2): 76-84 (2001) - [j8]Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev:
Design for Delay Testability in High-Speed Digital ICs. J. Electron. Test. 17(3-4): 225-231 (2001) - [c17]James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED 2001: 147-152 - [c16]Muhammad Nummer, Manoj Sachdev:
A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency. VTS 2001: 68-74 - 2000
- [c15]Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani:
Bridging the testing speed gap: design for delay testability. ETW 2000: 3-8 - [c14]Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC 2000: 1051-1059 - [c13]Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev:
A Low-Speed BIST Framework for High-Performance Circuit Testing. VTS 2000: 349-358
1990 – 1999
- 1999
- [j7]Manoj Sachdev, Hans G. Kerkhoff:
Configurations for IDDQ-Testable PLAs. IEEE Des. Test Comput. 16(2): 58-65 (1999) - [j6]Richard Rosing, Hans G. Kerkhoff, Ronald J. W. T. Tangelder, Manoj Sachdev:
Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters. J. Electron. Test. 14(1-2): 67-74 (1999) - [c12]Mansour Shashaani, Manoj Sachdev:
A DFT technique for high performance circuit testing. ITC 1999: 276-285 - 1998
- [c11]Manoj Sachdev, Peter Janssen, Victor Zieren:
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. ITC 1998: 204 - 1997
- [j5]Manoj Sachdev:
Open Defects in CMOS RAM Address Decoders. IEEE Des. Test Comput. 14(2): 26-33 (1997) - [c10]Manoj Sachdev:
Deep sub-micron IDDQ testing: issues and solutions. ED&TC 1997: 271-278 - 1996
- [j4]Manoj Sachdev:
SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis. J. Electron. Test. 8(2): 203-214 (1996) - [c9]Manoj Sachdev:
Test and Testability Techniques for Open Defects in RAM Address Decoders. ED&TC 1996: 428-434 - [c8]Rafael Llopis, Manoj Sachdev:
Low power, testable dual edge triggered flip-flops. ISLPED 1996: 341-345 - [c7]Manoj Sachdev:
Deep Sub-micron IDDQ Test Options. ITC 1996: 942 - 1995
- [j3]Manoj Sachdev:
Testing Defects in Scan Chains. IEEE Des. Test Comput. 12(4): 45-51 (1995) - [j2]Manoj Sachdev:
Reducing the CMOS RAM test complexity withIDDQ and voltage testing. J. Electron. Test. 6(2): 191-202 (1995) - [j1]Manoj Sachdev:
A realistic defect oriented testability methodology for analog circuits. J. Electron. Test. 6(3): 265-276 (1995) - [c6]F. C. M. Kuijstermans, Manoj Sachdev, A. P. Thijssen:
Defect-oriented test methodology for complex mixed-signal circuits. ED&TC 1995: 18-23 - [c5]Manoj Sachdev, Bert Atzema:
Industrial Relevance of Analog IFA: A Fact or a Fiction. ITC 1995: 61-70 - [c4]Manoj Sachdev:
IDDQ and Voltage Testable CMOS Flip-flop Configurations. ITC 1995: 534-543 - 1994
- [c3]Manoj Sachdev:
Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing. EDAC-ETC-EUROASIC 1994: 361-365 - 1993
- [c2]Manoj Sachdev:
Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier. DFT 1993: 319-326 - [c1]Manoj Sachdev, Math Verstraelen:
Development of Fault Model and Test Algorithms for Embedded DRAMs. ITC 1993: 815-824
Coauthor Index
Pierce Chuang
aka: Pierce I-Jen Chuang
aka: Pierce I-Jen Chuang
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-09-21 23:38 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
