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Jin-Fa Lin
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2020 – today
- 2022
- [j13]Jin-Fa Lin, Zheng-Jie Hong, Jun-Ting Wu, Xin-You Tung, Cheng-Hsueh Yang, Yu-Cheng Yen:
Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design. Sensors 22(15): 5696 (2022) - 2021
- [j12]Ming-Hwa Sheu, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin, Jin-Fa Lin:
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications. Sensors 21(19): 6591 (2021) - [c9]Zhi-Zhong Wang, Yi-Hsuan Hung, Jun-Ting Wu, Zheng-Jie Hong, Jin-Fa Lin:
A 0.5V True-Single-Phase 16T Flip-Flop in 180-nm CMOS for IoT Applications. ICCE-TW 2021: 1-2 - 2020
- [c8]Ching-Sheng Chang, Jin-Fa Lin, Ming-Ching Lee, Christoph Palm:
Semantic Lung Segmentation Using Convolutional Neural Networks. Bildverarbeitung für die Medizin 2020: 75-80
2010 – 2019
- 2019
- [j11]Po-Yu Kuo, Chia-Hsin Hsieh, Jin-Fa Lin, Ming-Hwa Sheu, Yi-Ting Hung:
Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design. IEICE Trans. Electron. 102-C(11): 833-838 (2019) - [c7]Wei-Hsuan Ma, Kuan-Ying Chang, Kuan-Ting Chen, Yin-Tsung Hwang, Jin-Fa Lin:
Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation. ISOCC 2019: 109-110 - 2018
- [c6]Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu:
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. ISCAS 2018: 1-4 - 2017
- [j10]Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai:
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3033-3044 (2017) - 2016
- [j9]Jin-Fa Lin, Ming-Yan Tsai, Kun-Sheng Li, Yun-Rong Jiang, Yu-Shiang Cheng:
Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors. J. Low Power Electron. 12(2): 112-116 (2016) - [c5]Shin-Shiang Wang, Yi-Chi Tien, Yin-Tsung Hwang, Jin-Fa Lin, Guo-Zua Wu:
MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging. APCCAS 2016: 143-145 - 2014
- [j8]Jin-Fa Lin:
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 181-185 (2014) - 2012
- [j7]Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu:
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 361-366 (2012) - [j6]Yin-Tsung Hwang, Jin-Fa Lin:
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1738-1742 (2012) - [c4]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
Low power 10-transistor full adder design based on degenerate pass transistor logic. ISCAS 2012: 496-499 - 2010
- [j5]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(4): 843-845 (2010) - [j4]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
Low Power Pulse Generator Design Using Hybrid Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1266-1268 (2010) - [j3]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2755-2757 (2010)
2000 – 2009
- 2008
- [j2]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu:
Low Complexity Dual-Mode Pulse Generator Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(7): 1812-1815 (2008) - 2007
- [j1]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho:
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(5): 1050-1059 (2007) - [c3]Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu:
Low Power Multipliers Using Enhenced Row Bypassing Schemes. SiPS 2007: 136-141 - 2006
- [c2]Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu:
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. APCCAS 2006: 594-597 - [c1]Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho:
A high speed and energy efficient full adder design using complementary & level restoring carry logic. ISCAS 2006
Coauthor Index
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