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ORCIDSavithri Sundareswaran
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2010 – 2019
- 2019
[j5]Weicheng Liu, Can Sitik
, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang:
SLECTS: Slew-Driven Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 864-874 (2019)- 2015
- [j4]Tong Xu, Peng Li, Savithri Sundareswaran:
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating. ACM Trans. Design Autom. Electr. Syst. 20(3): 38:1-38:30 (2015) - 2011
- [c20]Savithri Sundareswaran, Robert L. Maziasz, Vladimir Rozenfeld, Mikhail Sotnikov, Mukhanov Konstantin:
A sensitivity-aware methodology to improve cell layouts for DFM guidelines. ISQED 2011: 431-436 - 2010
- [c19]Yongchan Ban, Savithri Sundareswaran, David Z. Pan:
Total sensitivity based dfm optimization of standard library cells. ISPD 2010: 113-120
2000 – 2009
- 2009
- [c18]Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal:
Characterization of sequential cells for constraint sensitivities. ISQED 2009: 74-79 - 2008
- [c17]Ben Gu, Kiran K. Gullapalli, Yun Zhang, Savithri Sundareswaran:
Faster statistical cell characterization using adjoint sensitivity analysis. CICC 2008: 229-232 - [c16]Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran:
Transistor-Specific Delay Modeling for SSTA. DATE 2008: 592-597 - [c15]Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda:
Characterization of Standard Cells for Intra-Cell Mismatch Variations. ISQED 2008: 213-219 - [c14]Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham:
A timing methodology considering within-die clock skew variations. SoCC 2008: 351-356 - 2007
- [c13]Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan:
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. DAC 2007: 162-167 - [c12]Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao:
A novel technique for incremental analysis of on-chip power distribution networks. ICCAD 2007: 817-823 - [c11]Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham:
Small-Delay Defect Detection in the Presence of Process Variations. ISQED 2007: 711-716 - [c10]Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir:
Analyzing the risk of timing modeling based on path delay tests. ITC 2007: 1-10 - 2006
- [j3]Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power-supply pads and pins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 144-154 (2006) - [c9]Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu:
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. DAC 2006: 217-222 - 2004
- [c8]Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power supply pads and pins. DAC 2004: 165-170 - [c7]Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
A stochastic approach To power grid analysis. DAC 2004: 171-176 - 2003
- [j2]Rajendran Panda, Savithri Sundareswaran, David T. Blaauw:
Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Des. Test Comput. 20(3): 16-22 (2003) - [c6]Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda:
Statistical delay computation considering spatial correlations. ASP-DAC 2003: 271-276 - [c5]Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192 - 2002
- [j1]David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran:
Slope propagation in static timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1180-1195 (2002) - 2001
- [c4]Rajendran Panda, Savithri Sundareswaran, David T. Blaauw:
On the interaction of power distribution network with substrate. ISLPED 2001: 388-393 - 2000
- [c3]David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda:
Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343 - [c2]Savithri Sundareswaran, R. Venkatesan, S. Bhaskar:
An Assertion Based Technique for Transistor Level Dynamic Power Estimation. VLSI Design 2000: 34-37
1990 – 1999
- 1999
- [c1]Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury:
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design 1999: 175-180
Coauthor Index
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