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ORCIDChris C. N. Chu
Chris Chu – Chris Chong-Nuen Chu
Person information
- affiliation: Iowa State University, Ames, Iowa, USA
Other persons with a similar name
- Chris W. L. Chu (aka: Chris Wai Lung Chu) — University of Surrey, Guildford, UK
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2020 – today
- 2022
[c82]Chung-Hsien Wu
, Wai-Kei Mak, Chris Chu:
Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement. ISPD 2022: 211-218- 2021
- [c81]Tianxiang Gao, Songtao Lu, Jia Liu, Chris Chu:
On the Convergence of Randomized Bregman Coordinate Descent for Non-Lipschitz Composite Problems. ICASSP 2021: 5549-5553 - 2020
- [j47]Ankur Sharma, David G. Chinnery, Tiago Reimann, Sarvesh Bhardwaj, Chris Chu:
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1456-1469 (2020) - [i3]Tianxiang Gao, Songtao Lu, Jia Liu, Chris Chu:
Randomized Bregman Coordinate Descent Methods for Non-Lipschitz Optimization. CoRR abs/2001.05202 (2020)
2010 – 2019
- 2019
- [j46]Rohit Reddy Takkala, Chris Chu:
CHIP: Clustering Hotspots in Layout Using Integer Programming. J. Electr. Comput. Eng. 2019: 9430593:1-9430593:12 (2019) - [c80]Ankur Sharma, David G. Chinnery, Chris Chu:
Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach. ISPD 2019: 129-137 - [i2]Tianxiang Gao, Songtao Lu, Jia Liu, Chris Chu:
Leveraging Two Reference Functions in Block Bregman Proximal Gradient Descent for Non-convex and Non-Lipschitz Problems. CoRR abs/1912.07527 (2019) - 2018
- [j45]Yixiao Ding, Chris Chu, Wai-Kei Mak:
Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 657-668 (2018) - [j44]Hsin-Ho Huang, Huimei Cheng, Chris Chu, Peter A. Beerel:
Area Optimization of Timing Resilient Designs Using Resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1197-1210 (2018) - [j43]Chris Chu, Mustafa Ozdal:
Introduction to the Special Section on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. 23(4): 41:1-41:2 (2018) - [c79]Tianxiang Gao, Chris Chu:
DID: Distributed Incremental Block Coordinate Descent for Nonnegative Matrix Factorization. AAAI 2018: 2991-2998 - [c78]Chris Chu:
Pioneer Research on Mathematical Models and Methods for Physical Design. ISPD 2018: 126-129 - [e2]Chris Chu, Ismail Bustany:
Proceedings of the 2018 International Symposium on Physical Design, ISPD 2018, Monterey, CA, USA, March 25-28, 2018. ACM 2018 [contents] - [i1]Tianxiang Gao, Chris Chu:
DID: Distributed Incremental Block Coordinate Descent for Nonnegative Matrix Factorization. CoRR abs/1802.08938 (2018) - 2017
- [j42]Wai-Kei Mak, Wan-Sin Kuo, Shi-Han Zhang, Seong-I Lei, Chris Chu:
Minimum Implant Area-Aware Placement and Threshold Voltage Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1103-1112 (2017) - [j41]Yixiao Ding, Chris Chu, Wai-Kei Mak:
Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1381-1394 (2017) - [j40]Gang Wu, Chris Chu:
Two Approaches for Timing-Driven Placement by Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2093-2105 (2017) - [c77]Ankur Sharma, David G. Chinnery, Shrirang Dhamdhere, Chris Chu:
Rapid gate sizing with fewer iterations of Lagrangian Relaxation. ICCAD 2017: 337-343 - [c76]Gang Wu, Chris Chu:
A Fast Incremental Cycle Ratio Algorithm. ISPD 2017: 75-82 - [c75]Yixiao Ding, Chris Chu, Wai-Kei Mak:
Pin Accessibility-Driven Detailed Placement Refinement. ISPD 2017: 133-140 - [e1]Mustafa Ozdal, Chris Chu:
Proceedings of the 2017 ACM on International Symposium on Physical Design, ISDP 2017, Portland, OR, USA, March 19-22, 2017. ACM 2017, ISBN 978-1-4503-4696-2 [contents] - 2016
- [j39]Gang Wu, Chris Chu:
Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1569-1573 (2016) - [c74]Seong-I Lei, Wai-Kei Mak, Chris Chu:
Minimum implant area-aware placement and threshold voltage refinement. ASP-DAC 2016: 192-197 - [c73]Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak:
Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration. DAC 2016: 42:1-42:6 - [c72]Gang Wu, Yue Xu, Dean Wu, Manoj Ragupathy, Yu-Yen Mo, Chris C. N. Chu:
Flip-flop clustering by weighted K-means algorithm. DAC 2016: 82:1-82:6 - [c71]Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel:
Area optimization of resilient designs guided by a mixed integer geometric program. DAC 2016: 130:1-130:6 - [c70]Gang Wu, Chris C. N. Chu:
Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits. DATE 2016: 1042-1047 - [r5]Chris Chu:
Block Shaping in Floorplan. Encyclopedia of Algorithms 2016: 223-227 - [r4]Chris Chu:
Wire Sizing. Encyclopedia of Algorithms 2016: 2374-2378 - 2015
- [j38]Tao Lin, Chris C. N. Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev:
POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 447-459 (2015) - [j37]Chris C. N. Chu, Wai-Kei Mak:
Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(10): 1652-1663 (2015) - [c69]Gang Wu, Ankur Sharma, Chris C. N. Chu:
Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation. ASYNC 2015: 53-60 - [c68]Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak:
Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography. DAC 2015: 69:1-69:6 - [c67]Yixiao Ding, Chris C. N. Chu, Xin Zhou:
An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT. DAC 2015: 72:1-72:6 - [c66]Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu:
Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. ICCAD 2015: 426-433 - [c65]Tao Lin, Chris C. N. Chu, Gang Wu:
POLAR 3.0: An Ultrafast Global Placement Engine. ICCAD 2015: 520-527 - [c64]Tao Lin, Chris C. N. Chu:
TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring Constraints. ISPD 2015: 75-80 - 2014
- [j36]Wai-Kei Mak, Chris Chu:
E-Beam Lithography Character and Stencil Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 741-751 (2014) - [j35]Jackey Z. Yan, Natarajan Viswanathan, Chris Chu:
An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs. ACM Trans. Design Autom. Electr. Syst. 19(3): 29:1-29:25 (2014) - [c63]Chris Chu, Wai-Kei Mak:
Flexible packed stencil design with multiple shaping apertures for e-beam lithography. ASP-DAC 2014: 137-142 - [c62]Yixiao Ding, Chris Chu, Wai-Kei Mak:
Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout. DAC 2014: 51:1-51:6 - [c61]Tao Lin, Chris Chu:
POLAR 2.0: An Effective Routability-Driven Placer. DAC 2014: 123:1-123:6 - [c60]Gang Wu, Tao Lin, Hsin-Ho Huang, Chris Chu, Peter A. Beerel:
Asynchronous circuit placement by lagrangian relaxation. ICCAD 2014: 641-646 - [c59]Seong-I Lei, Chris Chu, Wai-Kei Mak:
Double patterning-aware detailed routing with mask usage balancing. ISQED 2014: 219-223 - 2013
- [j34]J. Morris Chang, Chi-Chen Fang, Kuan-Hsing Ho, Norene Kelly, Pei Yuan Wu, Yixiao Ding, Chris Chu, Stephen B. Gilbert, Ahmed E. Kamal, Sun-Yuan Kung:
Capturing Cognitive Fingerprints from Keystroke Dynamics. IT Prof. 15(4): 24-28 (2013) - [j33]Jackey Z. Yan, Chris Chu:
SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 175-188 (2013) - [j32]Yanheng Zhang, Chris Chu:
RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1655-1668 (2013) - [j31]Yanheng Zhang, Chris Chu:
Fast and Effective Placement Refinement for Routability. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1751-1756 (2013) - [c58]Tao Lin, Chris Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev:
POLAR: placement based on novel rough legalization and refinement. ICCAD 2013: 357-362 - 2012
- [j30]Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang:
Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1711-1722 (2012) - [j29]Wai-Kei Mak, Chris Chu:
Rethinking the Wirelength Benefit of 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2346-2351 (2012) - [j28]Xin Zhao, Chris Chu:
Line Search-Based Inverse Lithography Technique for Mask Design. VLSI Design 2012: 589128:1-589128:9 (2012) - [j27]Min Pan, Yue Xu, Yanheng Zhang, Chris Chu:
FastRoute: An Efficient and High-Quality Global Router. VLSI Design 2012: 608362:1-608362:18 (2012) - [c57]Yanheng Zhang, Chris Chu:
GDRouter: interleaved global routing and detailed routing for ultimate routability. DAC 2012: 597-602 - [c56]Jackey Z. Yan, Chris Chu:
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning. ISPD 2012: 179-186 - 2011
- [j26]Gaurav Ajwani, Chris Chu, Wai-Kei Mak:
FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 194-204 (2011) - [j25]Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak:
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7): 1020-1033 (2011) - [c55]Yue Xu, Chris Chu:
MGR: Multi-level global router. ICCAD 2011: 250-255 - [c54]Yanheng Zhang, Chris Chu:
RegularRoute: an efficient detailed router with regular routing patterns. ISPD 2011: 45-52 - 2010
- [j24]Jackey Z. Yan, Chris Chu:
DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 367-381 (2010) - [c53]Yue Xu, Chris Chu:
An auction based pre-processing technique to determine detour in global routing. ICCAD 2010: 305-311 - [c52]Gaurav Ajwani, Chris Chu, Wai-Kei Mak:
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. ISPD 2010: 27-34 - [c51]Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu:
ITOP: integrating timing optimization within placement. ISPD 2010: 83-90 - [c50]Yue Xu, Chris Chu:
A matching based decomposer for double patterning lithography. ISPD 2010: 121-126 - [c49]Jackey Z. Yan, Chris Chu, Wai-Kei Mak:
SafeChoice: a novel clustering algorithm for wirelength-driven placement. ISPD 2010: 185-192
2000 – 2009
- 2009
- [j23]Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu:
Handling routability in floorplan design with twin binary trees. Integr. 42(4): 449-456 (2009) - [c48]Yue Xu, Yanheng Zhang, Chris Chu:
FastRoute 4.0: global router with efficient via minimization. ASP-DAC 2009: 576-581 - [c47]Jackey Z. Yan, Natarajan Viswanathan, Chris Chu:
Handling complexities in modern large-scale mixed-size placement. DAC 2009: 436-441 - [c46]Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang:
Pad assignment for die-stacking System-in-Package design. ICCAD 2009: 249-255 - [c45]Yanheng Zhang, Chris Chu:
CROP: Fast and effective congestion refinement of placement. ICCAD 2009: 344-350 - [c44]Yue Xu, Chris Chu:
GREMA: Graph reduction based efficient mask assignment for double patterning technology. ICCAD 2009: 601-606 - 2008
- [j22]Chris C. N. Chu, Yiu-Chung Wong:
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 70-83 (2008) - [c43]Jackey Z. Yan, Chris Chu:
DeFer: deferred decision making enabled fixed-outline floorplanner. DAC 2008: 161-166 - [c42]Yanheng Zhang, Yue Xu, Chris Chu:
FastRoute3.0: a fast and high quality global router based on virtual capacity. ICCAD 2008: 344-349 - [r3]Chris Chu:
Wire Sizing. Encyclopedia of Algorithms 2008 - [r2]Chris C. N. Chu, Min Pan:
Clock Network Design. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Chris C. N. Chu, Min Pan:
Practical Issues in Clock Network Design. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j21]Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu:
Wire Retiming Problem With Net Topology Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1648-1660 (2007) - [c41]Natarajan Viswanathan, Min Pan, Chris C. N. Chu:
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. ASP-DAC 2007: 135-140 - [c40]Min Pan, Chris C. N. Chu, Priyadarshan Patra:
A Novel Performance-Driven Topology Design Algorithm. ASP-DAC 2007: 244-249 - [c39]Min Pan, Chris C. N. Chu:
FastRoute 2.0: A High-quality and Efficient Global Router. ASP-DAC 2007: 250-255 - [c38]Min Pan, Chris C. N. Chu:
IPR: An Integrated Placement and Routing Algorithm. DAC 2007: 59-62 - [c37]Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu:
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458 - [c36]Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia:
The coming of age of physical synthesis. ICCAD 2007: 246-249 - [p1]Natarajan Viswanathan, Min Pan, Chris Chu:
FastPlace: An Efficient Multilevel Force-Directed Placement Algorithm. Modern Circuit Placement 2007: 193-228 - 2006
- [c35]Natarajan Viswanathan, Min Pan, Chris C. N. Chu:
FastPlace 2.0: an efficient analytical placer for mixed-mode designs. ASP-DAC 2006: 195-200 - [c34]Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu:
Optimal cell flipping in placement and floorplanning. DAC 2006: 1109-1114 - [c33]Chuan Lin, Hai Zhou, Chris C. N. Chu:
A revisit to floorplan optimization by Lagrangian relaxation. ICCAD 2006: 164-171 - [c32]Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu:
Analog placement with symmetry and other placement constraints. ICCAD 2006: 349-354 - [c31]Min Pan, Chris C. N. Chu:
FastRoute: a step to integrate global routing into placement. ICCAD 2006: 464-471 - [c30]Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu:
Post-placement voltage island generation. ICCAD 2006: 641-646 - 2005
- [j20]Sampath Dechu, Zion Cien Shen, Chris C. N. Chu:
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 600-608 (2005) - [j19]Natarajan Viswanathan, Chris C. N. Chu:
FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 722-733 (2005) - [c29]Min Pan, Natarajan Viswanathan, Chris C. N. Chu:
An efficient and effective detailed placement algorithm. ICCAD 2005: 48-55 - [c28]Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li:
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. ICCD 2005: 38-44 - [c27]Min Pan, Chris C. N. Chu, J. Morris Chang:
Transition time bounded low-power clock tree construction. ISCAS (3) 2005: 2445-2448 - [c26]Min Pan, Chris C. N. Chu, Hai Zhou:
Timing yield estimation using statistical static timing analysis. ISCAS (3) 2005: 2461-2464 - [c25]Chris C. N. Chu, Yiu-Chung Wong:
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. ISPD 2005: 28-35 - [c24]Natarajan Viswanathan, Min Pan, Chris C. N. Chu:
FastPlace: an analytical placer for mixed-mode designs. ISPD 2005: 221-223 - 2004
- [j18]Chris C. N. Chu, Evangeline F. Y. Young:
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 71-79 (2004) - [j17]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 136-141 (2004) - [j16]Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu:
Fitted Elmore delay: a simple and accurate interconnect delay model. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 691-696 (2004) - [j15]Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho:
Placement constraints in floorplan design. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 735-745 (2004) - [c23]Sampath Dechu, Zion Cien Shen, Chris C. N. Chu:
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. ASP-DAC 2004: 361-366 - [c22]Zion Cien Shen, Chris C. N. Chu:
Accurate and efficient flow based congestion estimation in floorplanning. ASP-DAC 2004: 671-676 - [c21]Chris Chu:
FLUTE: fast lookup table based wirelength estimation technique. ICCAD 2004: 696-701 - [c20]Natarajan Viswanathan, Chris C. N. Chu:
FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. ISPD 2004: 26-33 - [c19]Debjit Sinha, Hai Zhou, Chris C. N. Chu:
Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181 - 2003
- [j14]Daniel Berleant, Mei-Peng Cheong, Chris C. N. Chu, Yong Guan, Ahmed E. Kamal, Gerald Shedblé, Scott Ferson, James F. Peters:
Dependable Handling of Uncertainty. Reliab. Comput. 9(6): 407-418 (2003) - [j13]Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen:
Twin binary sequences: a nonredundant representation for general nonslicing floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 457-469 (2003) - [j12]Zion Cien Shen, Chris C. N. Chu:
Bounds on the number of slicing, mosaic, and general floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1354-1361 (2003) - [c18]Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu:
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. DATE 2003: 10856-10861 - [c17]Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu:
Retiming with Interconnect and Gate Delay. ICCAD 2003: 221-226 - [c16]Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz:
Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC 2003: 180-185 - [c15]Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz:
Optimizing SOC Test Resources Using Dual Sequences. VLSI-SoC (Selected Papers) 2003: 181-196 - 2002
- [c14]Chris C. N. Chu, Evangeline F. Y. Young:
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. DATE 2002: 1101 - [c13]Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu:
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. ICCD 2002: 422-427 - [c12]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109 - [c11]Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen:
Twin binary sequences: a non-redundant representation for general non-slicing floorplan. ISPD 2002: 196-201 - [c10]Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho:
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. ASP-DAC/VLSI Design 2002: 661- - 2001
- [j11]Chris C. N. Chu, D. F. Wong:
VLSI Circuit Performance Optimization by Geometric Programming. Ann. Oper. Res. 105(1-4): 37-60 (2001) - [j10]Yu-Yen Mo, Chris C. N. Chu:
Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 680-686 (2001) - [j9]Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong:
Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 687-692 (2001) - [j8]Chris C. N. Chu, D. F. Wong:
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6(3): 343-371 (2001) - 2000
- [c9]Yu-Yen Mo, Chris C. N. Chu:
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. ISPD 2000: 134-139 - [c8]Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong:
Floorplan area minimization using Lagrangian relaxation. ISPD 2000: 174-179
1990 – 1999
- 1999
- [j7]Fung Yu Young, Chris C. N. Chu, D. F. Wong:
Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999) - [j6]Chris C. N. Chu, Martin D. F. Wong:
Greedy wire-sizing is linear time. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 398-405 (1999) - [j5]Chris C. N. Chu, Martin D. F. Wong:
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 787-798 (1999) - [j4]Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong:
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 1014-1025 (1999) - [j3]Chris C. N. Chu, Martin D. F. Wong:
An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1297-1304 (1999) - 1998
- [j2]Chris C. N. Chu, Martin D. F. Wong:
A matrix synthesis approach to thermal placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1166-1174 (1998) - [c7]Chris C. N. Chu, D. F. Wong:
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE 1998: 479-485 - [c6]Chung-Ping Chen, Chris C. N. Chu, D. F. Wong:
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624 - [c5]Chris C. N. Chu, D. F. Wong:
Greedy wire-sizing is linear time. ISPD 1998: 39-44 - 1997
- [c4]Chris C. N. Chu, D. F. Wong:
A new approach to simultaneous buffer insertion and wire sizing. ICCAD 1997: 614-621 - [c3]Chris C. N. Chu, D. F. Wong:
A matrix synthesis approach to thermal placement. ISPD 1997: 163-168 - [c2]Chris C. N. Chu, D. F. Wong:
Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD 1997: 192-197 - 1996
- [j1]Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wei-Kei Mak:
Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. J. Parallel Distributed Comput. 33(1): 98-106 (1996) - 1993
- [c1]Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wai-Kei Mak:
Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. SPDP 1993: 285-289
Coauthor Index
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last updated on 2024-07-26 18:47 CEST by the dblp team
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