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ORCIDDonald E. Thomas
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- affiliation: Carnegie Mellon University, Pittsburgh, USA
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2010 – 2019
- 2017
[c67]Xiang Lin, R. D. (Shawn) Blanton, Donald E. Thomas:
Random Forest Architectures on FPGA for Multiple Applications. ACM Great Lakes Symposium on VLSI 2017: 415-418- 2015
- [c66]Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu
, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas:
Statistical Learning in Chip (SLIC). ICCAD 2015: 664-669 - [c65]Donald E. Thomas:
Keynote speaker moving digital system design courses into the modern era, again. MSE 2015 - 2014
- [j25]Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
Cost-effective lifetime and yield optimization for NoC-based MPSoCs. ACM Trans. Design Autom. Electr. Syst. 19(2): 12:1-12:33 (2014) - [c64]Minho Won, Hassan Albalawi, Xin Li, Donald E. Thomas:
Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform. EMBC 2014: 1626-1629 - [c63]Xin Li, Ronald Shawn Blanton, Pulkit Grover, Donald E. Thomas:
Ultra-low-power biomedical circuit design and optimization: Catching the don't cares. ISIC 2014: 115-118 - [c62]Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas:
SLIC: Statistical learning in chip. ISIC 2014: 119-123 - 2012
- [c61]Adam S. Hartman, Donald E. Thomas:
Lifetime improvement through runtime wear-based task mapping. CODES+ISSS 2012: 13-22 - 2010
- [j24]Alex Bobrek, JoAnn M. Paul, Donald E. Thomas:
Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors. IEEE Trans. Computers 59(10): 1402-1418 (2010) - [c60]Adam S. Hartman, Donald E. Thomas, Brett H. Meyer:
A case for lifetime-aware task mapping in embedded chip multiprocessors. CODES+ISSS 2010: 145-154 - [c59]Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. DATE 2010: 1596-1601 - [c58]Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
Slack allocation for yield improvement in NoC-based MPSoCs. ISQED 2010: 738-746
2000 – 2009
- 2009
- [j23]Brett H. Meyer, Donald E. Thomas:
Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC. Des. Autom. Embed. Syst. 13(1-2): 73-88 (2009) - 2007
- [c57]Brett H. Meyer, Donald E. Thomas:
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. CODES+ISSS 2007: 3-8 - [c56]Alex Bobrek, JoAnn M. Paul, Donald E. Thomas:
Event-based re-training of statistical contention models for heterogeneous multiprocessors. CODES+ISSS 2007: 69-74 - [c55]Alex Bobrek, JoAnn M. Paul, Donald E. Thomas:
Shared Resource Access Attributes for High-Level Contention Models. DAC 2007: 720-725 - [c54]Brett H. Meyer, Donald E. Thomas:
Rethinking Automated Synthesis of MPSoC Architectures. IPDPS 2007: 1-6 - 2006
- [j22]JoAnn M. Paul, Donald E. Thomas, Alex Bobrek:
Scenario-oriented design for single-chip heterogeneous multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 14(8): 868-880 (2006) - 2005
- [j21]Philip Koopman, Howie Choset, Rajeev Gandhi, Bruce H. Krogh, Diana Marculescu, Priya Narasimhan, JoAnn M. Paul, Ragunathan Rajkumar, Daniel P. Siewiorek, Asim Smailagic, Peter Steenkiste, Donald E. Thomas, Chenxi Wang:
Undergraduate embedded system education at Carnegie Mellon. ACM Trans. Embed. Comput. Syst. 4(3): 500-528 (2005) - [j20]JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy:
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Design Autom. Electr. Syst. 10(3): 431-461 (2005) - 2004
- [c53]JoAnn M. Paul, Donald E. Thomas, Alex Bobrek:
Benchmark-based design strategies for single chip heterogeneous multiprocessors. CODES+ISSS 2004: 54-59 - [c52]Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim:
High level cache simulation for heterogeneous multiprocessors. DAC 2004: 287-292 - [c51]Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas:
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. DATE 2004: 1144-1149 - 2003
- [c50]JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas:
Schedulers as model-based design elements in programmable heterogeneous multiprocessors. DAC 2003: 408-411 - [c49]Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas:
Layered, Multi-Threaded, High-Level Performance Design. DATE 2003: 10954-10959 - 2002
- [c48]JoAnn M. Paul, Christopher M. Eatedali, Donald E. Thomas:
The design context of concurrent computation systems. CODES 2002: 19-24 - [c47]JoAnn M. Paul, Donald E. Thomas:
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. DATE 2002: 522-528 - [c46]JoAnn M. Paul, Arne J. Suppé, Henele I. Adams, Donald E. Thomas:
Multi-Level Modeling of Software on Hardware in Concurrent Computation. IPDPS 2002 - [c45]Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul:
System-Level Modeling of a Network Switch SoC. ISSS 2002: 62-67 - 2001
- [j19]Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas:
Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 805-812 (2001) - [c44]Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas:
Modeling and evaluation of hardware/software designs. CODES 2001: 11-16 - [c43]JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas:
Modeling and simulation of steady state and transient behaviors for emergent SoCs. ISSS 2001: 262-267 - 2000
- [j18]Sari L. Coumeri, Donald E. Thomas:
Memory modeling for system synthesis. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 327-334 (2000) - [c42]JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas:
Frequency interleaving as a codesign scheduling paradigm. CODES 2000: 131-135 - [c41]JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas:
A codesign virtual machine for hierarchical, balanced hardware/software system modeling. DAC 2000: 390-395 - [c40]William E. Dougherty, Donald E. Thomas:
Unifying behavioral synthesis and physical design. DAC 2000: 756-761
1990 – 1999
- 1999
- [j17]William E. Dougherty, David J. Pursley, Donald E. Thomas:
Subsetting Behavioral Intellectual Property for Low Power ASIP Design. J. VLSI Signal Process. 21(3): 209-218 (1999) - [c39]Donald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber:
Peer-based multithreaded executable co-specification. CODES 1999: 105-109 - [c38]Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass:
Vertical Benchmarks for CAD. DAC 1999: 408-413 - [c37]Sari L. Coumeri, Donald E. Thomas:
An Environment for Exploring Low Power Memory Configurations in System Level Design. ICCD 1999: 348-353 - [c36]William E. Dougherty, Donald E. Thomas:
Modeling and automating selection of guarding techniques for datapath elements. ISLPED 1999: 182-187 - 1998
- [j16]Herman Schmit, Donald E. Thomas:
Address generation for memories containing multiple arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5): 377-385 (1998) - [c35]Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas:
Managing Pipeline-Reconfigurable FPGAs. FPGA 1998: 55-64 - [c34]Sari L. Coumeri, Donald E. Thomas:
Memory modeling for system synthesis. ISLPED 1998: 179-184 - 1997
- [j15]Herman Schmit, Donald E. Thomas:
Synthesis of application-specific memory designs. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 101-111 (1997) - 1996
- [b2]Donald E. Thomas, Philip Moorby:
The Verilog hardware description language (3. ed.). Kluwer 1996, ISBN 978-0-7923-9723-6, pp. I-XVI, 1-310 - [c33]Jay K. Adams, Donald E. Thomas:
The Design of Mixed Hardware/Software Systems. DAC 1996: 515-520 - 1995
- [b1]Donald E. Thomas, Philip Moorby:
The Verilog hardware description language (2. ed.). Kluwer 1995, ISBN 978-0-7923-9523-2, pp. I-XVI, 1-275 - [c32]Prashant Sawkar, Donald E. Thomas:
Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. DAC 1995: 201-205 - [c31]Herman Schmit, Donald E. Thomas:
Hidden Markov modeling and fuzzy controllers in FPGAs. FCCM 1995: 214-221 - [c30]Herman Schmit, Donald E. Thomas:
Address generation for memories containing multiple arrays. ICCAD 1995: 510-514 - [c29]Jay K. Adams, John Alan Miller, Donald E. Thomas:
Execution-time profiling for multiple-process behavioral synthesis. ICCD 1995: 144-149 - [c28]Jay K. Adams, Donald E. Thomas:
Multiple-process behavioral synthesis for mixed hardware-software systems. ISSS 1995: 10-15 - [c27]Herman Schmit, Donald E. Thomas:
Array mapping in behavioral synthesis. ISSS 1995: 90-95 - 1994
- [j14]D. L. Springer, Donald E. Thomas:
Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 843-856 (1994) - [c26]Lawrence F. Arnstein, Donald E. Thomas:
The Attributed-Behavior Abstraction and Synthesis Tools. DAC 1994: 557-561 - [c25]Lawrence F. Arnstein, Donald E. Thomas:
Applications of attributed-behavior synthesis. HLSS 1994: 29-34 - [c24]R. S. Ramchandani, Donald E. Thomas:
Behavioral-Test Generation using Mixed-Integer Non-linear Programming. ITC 1994: 958-967 - 1993
- [j13]Donald E. Thomas, Jay K. Adams, Herman Schmit:
A Model and Methodology for Hardware-Software Codesign. IEEE Des. Test Comput. 10(3): 6-15 (1993) - [j12]Anthony J. Gadient, Donald E. Thomas:
A dynamic approach to controlling high-level synthesis CAD tools. IEEE Trans. Very Large Scale Integr. Syst. 1(3): 328-341 (1993) - [c23]Prashant Sawkar, Donald E. Thomas:
Performance Directed Technology Mapping for Look-Up Table Based FPGAs. DAC 1993: 208-212 - [c22]Richard J. Cloutier, Donald E. Thomas:
Synthesis of Pipelined Instruction Set Processors. DAC 1993: 583-588 - [c21]Lawrence F. Arnstein, Donald E. Thomas:
A general consistency technique for increasing the controllability of high level synthesis tools. ICCAD 1993: 741-744 - 1992
- [c20]Prashant Sawkar, Donald E. Thomas:
Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. DAC 1992: 368-373 - [c19]Jay K. Adams, Donald E. Thomas:
Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. ICCD 1992: 194-197 - 1991
- [j11]David Springer, Donald E. Thomas:
New methods for coloring and clique partitioning in data path allocation. Integr. 12(3): 267-292 (1991) - [j10]Elizabeth D. Lagnese, Donald E. Thomas:
Architectural partitioning for system level synthesis of integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7): 847-860 (1991) - 1990
- [c18]Richard J. Cloutier, Donald E. Thomas:
The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. DAC 1990: 71-76 - [c17]D. L. Springer, Donald E. Thomas:
Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. ICCAD 1990: 254-257
1980 – 1989
- 1989
- [j9]Robert A. Walker, Donald E. Thomas:
Behavioral transformation for algorithmic level IC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10): 1115-1128 (1989) - [c16]Elizabeth D. Lagnese, Donald E. Thomas:
Architectural Partitioning for System Level Design. DAC 1989: 62-67 - [e1]Donald E. Thomas:
Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989. ACM Press 1989 [contents] - 1988
- [c15]Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn:
The System Architect's Workbench. DAC 1988: 337-343 - [c14]Robert L. Blackburn, Donald E. Thomas, Patti M. Koenig:
CORAL II: Linking Behavior and Structure in an IC Design System. DAC 1988: 529-535 - 1987
- [j8]Donald E. Thomas, Robert L. Blackburn, Jayanth V. Rajan:
Linking the Behavioral and Structural Domains of Representation for Digital System Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(1): 103-110 (1987) - 1985
- [c13]Donald E. Thomas:
Observations on comparing digital systems synthesis techniques. ACM Conference on Computer Science 1985: 17-22 - [c12]Thaddeus J. Kowalski, Donald E. Thomas:
The VLSI design automation assistant: what's in a knowledge base. DAC 1985: 252-258 - [c11]Jayanth V. Rajan, Donald E. Thomas:
Synthesis by delayed binding of decisions. DAC 1985: 367-373 - [c10]Robert L. Blackburn, Donald E. Thomas:
Linking the behavioral and structural dominis of representation in a synthesis system. DAC 1985: 374-380 - [c9]Robert A. Walker, Donald E. Thomas:
A model of design representation and synthesis. DAC 1985: 453-459 - 1984
- [j7]Thaddeus J. Kowalski, Donald E. Thomas:
The VLSI Design Automation Assistant: An IBM System/370 Design. IEEE Des. Test 1(1): 60-69 (1984) - [j6]Richard M. Sedmak, Donald E. Thomas:
Probing the State of the Art. IEEE Des. Test 1(3): 18-19 (1984) - 1983
- [j5]Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker:
Automatic Data Path Synthesis. Computer 16(12): 59-70 (1983) - [j4]Donald E. Thomas, Gary W. Leive:
Automating Technology Relative Logic Synthesis and Module Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(2): 94-105 (1983) - [j3]Donald E. Thomas, John A. Nestor:
Defining and Implementing a Multilevel Design Representation with Simulation Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(3): 135-145 (1983) - [c8]Thaddeus J. Kowalski, Donald E. Thomas:
The VLSI Design Automation Assistant: Prototype system. DAC 1983: 479-483 - [c7]Charles Y. Hitchcock III, Donald E. Thomas:
A method of automatic data path synthesis. DAC 1983: 484-489 - [c6]Robert A. Walker, Donald E. Thomas:
Behavioral level transformation in the CMU-DA system. DAC 1983: 788-789 - 1982
- [c5]John A. Nestor, Donald E. Thomas:
Defining and implementing a multilevel design representation with simulation applications. DAC 1982: 740-746 - 1981
- [j2]Donald E. Thomas, Daniel P. Siewiorek:
Measuring Designer Performance to Verify Design Automation Systems. IEEE Trans. Computers 30(1): 48-61 (1981) - [c4]Gary W. Leive, Donald E. Thomas:
A technology relative Logic Synthesis and Module Selection system. DAC 1981: 479-485
1970 – 1979
- 1979
- [c3]Alice C. Parker, Donald E. Thomas, Daniel P. Siewiorek, Mario Barbacci, Louis J. Hafer, Gary W. Leive, Jinchoon Kim:
The CMU design automation system: An example of automated data path design. DAC 1979: 73-80 - 1978
- [j1]Daniel P. Siewiorek, Donald E. Thomas, Don L. Scharfetter:
The Use of LSI Modules in Computer Structures: Trends and Limitations. Computer 11(7): 16-25 (1978) - [c2]Edward A. Snow, Daniel P. Siewiorek, Donald E. Thomas:
A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs. DAC 1978: 220-226 - 1977
- [c1]Donald E. Thomas, Daniel P. Siewiorek:
Measuring designer performance to verify design automation systems. DAC 1977: 411-418
Coauthor Index
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