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ORCIDDATE 2024: Valencia, Spain
- Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024. IEEE 2024, ISBN 978-3-9819263-8-5
- Rafael Batista, Matthias Nickel, Alexander Lehnert, Sergio A. Pertuz, Marc Reichenbach, Diana Goehringer, Alisson Brito:
Towards an Embedded System for Failure Diagnosis in Drones Using AI and SAC-DM on FPGA. 1-2 - Vladimir Pesic, Andrew Wright, Edoardo Charbon:
From Master Equation to SPICE: A Platform to Model Cryo-CMOS Control for Qubits. 1-6 - Marcel Aguirre Mehlhorn, Hauke Dierend, Andreas Richter, Yuri A. W. Shardt:
A Stakeholder Analysis of Operational Design Domains of Automated Driving Systems. 1-2 - Sriram Vasudevan, Prasanna Ravi, Arpan Jati, Shivam Bhasin, Anupam Chattopadhyay:
Formal Verification of Secure Boot Process. 1-6 - Ziying Ni, Ayesha Khalid, Weiqiang Liu, Máire O'Neill:
Bitstream Fault Injection Attacks on CRYSTALS Kyber Implementations on FPGAs. 1-6 - Yintao He, Shixin Zhao, Songyun Qu, Huawei Li, Xiaowei Li, Ying Wang:
Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture. 1-6 - Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu:
Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLS. 1-6 - Christian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi
, Karl F. A. Friebel, Antonella Galizia, Matteo Grasso, Paulo Silva, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni, Burkhard Ringlein, Roberto Rocco, Katerina Slaninová, Tom Slooff, Stephanie Soldavini, Felix Suchert, Mattia Tibaldi, Beat Weiss, Christoph Hagleitner:
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach. 1-6 - Mohit Upadhyay, Rohan Juneja, Weng-Fai Wong, Li-Shiuan Peh:
NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator. 1-6 - Takefumi Koike, Hiromitsu Awano, Takashi Sato:
DNA-Based Similar Image Retrieval via Triplet Network-Driven Encoder. 1-2 - Rozhin Yasaei, Yasamin Moghaddas, Mohammad Abdullah Al Faruque:
IoT-GRAF: IoT Graph Learning-Based Anomaly and Intrusion Detection Through Multi-Modal Data Fusion. 1-6 - Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi:
DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems. 1-6 - Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. 1-6 - Yifei Zhou, Xuchu Huang, Jianyi Yang, Kai Ni, Hussam Amrouch, Cheng Zhuo, Xunzhao Yin:
Low Power and Temperature- Resilient Compute-In-Memory Based on Subthreshold-FeFET. 1-6 - Samuele Ruffino, Geethan Karunaratne, Michael Hersche, Luca Benini, Abu Sebastian, Abbas Rahimi:
Zero-Shot Classification Using Hyperdimensional Computing. 1-2 - Stefan Engels, Robert Wille:
Late Breaking Results: Iterative Design Automation for Train Control with Hybrid Train Detection. 1-2 - Shun Li, Ruiqi Chen, Enhao Tang, Yajing Liu, Jing Yang, Kun Wang:
S-LGCN: Software-Hardware Co-Design for Accelerating LightGCN. 1-6 - Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. 1-6 - Kuchul Jung, Jongseok Woo, Saibal Mukhopadhyay:
A Hardware Accelerated Autoencoder for RF Communication Using Short-Time-Fourier- Transform Assisted Convolutional Neural Network. 1-6 - Md. Shohidul Islam, Sankha Baran Dutta, Andres Marquez, Ihsen Alouani, Khaled N. Khasawneh:
Harnessing ML Privacy by Design Through Crossbar Array Non-Idealities. 1-2 - Haobo Liu, Zhengyang Qian, Wei Wu, Hongwei Ren, Zhiwei Liu, Leibin Ni:
AFPR-CIM: An Analog-Domain Floating-Point RRAM -based Compute- In- Memory Architecture with Dynamic Range Adaptive FP-ADC. 1-6 - Sofiane Takarabt, Javad Bahrami, Mohammad Ebrahimabadi, Sylvain Guilley, Naghmeh Karimi:
Securing ISW Masking Scheme Against Glitches. 1-2 - Tongxin Xie, Tianchen Zhao, Zhenhua Zhu, Xuefei Ning, Bing Li, Guohao Dai, Huazhong Yang, Yu Wang:
DyPIM: Dynamic-Inference-Enabled Processing - In-Memory Accelerator. 1-6 - Yifeng Xiao, Chanwook Oh, Michele Lora, Pierluigi Nuzzo:
Efficient Exploration of Cyber-Physical System Architectures Using Contracts and Subgraph Isomorphism. 1-6 - Caroline Dominik, Rolf Drechsler:
Polynomial Formal Verification of Sequential Circuits. 1-6 - Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications. 1-6 - Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux:
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. 1-6 - Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini:
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors. 1-6 - Yeshwanth Venkatesha, Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda:
HaLo-FL: Hardware-Aware Low-Precision Federated Learning. 1-6 - Bruno Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano, Marco Ottavi:
Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes. 1-2 - Tarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann:
ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates. 1-2 - Shuhan Bai, You Zhou, Fei Wu, Changsheng Xie, Tei-Wei Kuo, Chun Jason Xue:
LaVA: An Effective Layer Variation Aware Bad Block Management for 3D CT NAND Flash. 1-6 - Cristian Turetta, Philipp H. Kindt, Alejandro Masrur, Samarjit Chakraborty, Graziano Pravadelli, Florenc Demrozi:
Environmental Microchanges in WiFi Sensing. 1-2 - Amalia-Artemis Koufopoulou, Athanasios Papadimitriou, Mihalis Psarakis, David Hély:
Automated Hardware Security Countermeasure Integration Inside High Level Synthesis. 1-2 - Yuanzhang Wang, Peng Zhang, Fengkui Yang, Ke Zhou, Chunhua Li:
LoADM: Load-Aware Directory Migration Policy in Distributed File Systems. 1-6 - Mingyu Huang, Ji Guan, Wang Fang, Mingsheng Ying:
Approximation Algorithm for Noisy Quantum Circuit Simulation. 1-6 - Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini:
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. 1-6 - Bingcai Sui, Junzhong Shen, Caixia Sun, Junhui Wang, Zhong Zheng, Wei Guo:
MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-Core Processor. 1-6 - Sayeed Shafayet Chowdhury, Adarsh Kumar Kosta, Deepika Sharma, Marco Paul E. Apolinario, Kaushik Roy:
Unearthing the Potential of Spiking Neural Networks. 1-6 - Jianan Wen, Andrea Baroni, Eduardo Perez, Max Uhlmann, Markus Fritscher, Karthik KrishneGowda, Markus Ulbricht, Christian Wenger, Milos Krstic:
Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator. 1-6 - Ingu Jeong, Jun-Eun Park:
X-PIM: Fast Modeling and Validation Framework for Mixed-Signal Processing-in-Memory Using Compressed Equivalent Model in System Verilog. 1-6 - Weiyi Wang, Lang Feng, Zhiguo Shi, Cheng Zhuo, Jiming Chen:
Hardware-Assisted Control-Flow Integrity Enhancement for IoT Devices. 1-6 - Yang Zhang, Xiangrui Wang, Dong Jiang, Zhanhong Huang, Gaopeng Fan, Enyi Yao:
A Parallel Tempering Processing Architecture with Multi-Spin Update for Fully-Connected Ising Models. 1-6 - Zhenhua Tan, Linbo Long, Jingcheng Shen, Congming Gao, Renping Liu, Yi Jiang:
Para-ZNS: Improving Small-Zone ZNS SSDs Parallelism Through Dynamic Zone Mapping. 1-6 - Yuanxin Wei, Shengyuan Ye, Jiazhi Jiang, Xu Chen, Dan Huang, Jiangsu Du, Yutong Lu:
Communication-Efficient Model Parallelism for Distributed In-Situ Transformer Inference. 1-6 - Zhewen Yu, Christos-Savvas Bouganis:
Auto WS: Automate Weights Streaming in Layer-Wise Pipelined DNN Accelerators. 1-6 - Se-Min Lim, Sang-Woo Jun:
FlexForge: Efficient Reconfigurable Cloud Acceleration via Peripheral Resource Disaggregation. 1-6 - Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han, Xiaoming Chen:
PIMSYN: Synthesizing Processing-in-Memory CNN Accelerators. 1-6 - Yujin Lim, Dongwhee Kim, Jungrae Kim:
SELCC: Enhancing MLC Reliability and Endurance with Single-Cell Error Correction Codes. 1-6 - Mutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta:
A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. 1-2 - T. P. Abdul Rahoof, Vivek Chaturvedi, Mahesh Raveendranatha Panicker, Muhammad Shafique:
Tiny- VBF: Resource-Efficient Vision Transformer based Lightweight Beamformer for Ultrasound Single-Angle Plane Wave Imaging. 1-6 - Guangyu Wei, Changlong Li, Rui Xu, Qingfeng Zhuge, Edwin H.-M. Sha:
Sparrow: Flexible Memory Deduplication in Android Systems with Similar-Page Awareness. 1-6 - Zhenyu Guan, Yongqing Zhu, Yicheng Huang, Luchang Lei, Xueyan Wang, Hongyang Jia, Yi Chen, Bo Zhang, Jin Dong, Song Bian:
ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration. 1-6 - Shang-Hung Ti, Tseng-Yi Chen, Tsung Tai Yeh, Shuo-Han Chen, Yu-Pei Liang:
OC-DLRM: Minimizing the I/O Traffic of DLRM Between Main Memory and OCSSD. 1-2 - Emad Malekzadeh Arasteh, Vivek Govindasamy, Rainer Dömer:
BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0. 1-6 - Kavitha S, Binsu J. Kailath, Bhupendra Singh Reniwal:
CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks. 1-2 - Lukas Steiner, Timo Lehnigk-Emden, Markus Fehrenz, Norbert Wehn:
A Mapping of Triangular Block Interleavers to DRAM for Optical Satellite Communication. 1-2 - Lorenzo Sonnino, Shaswot Shresthamali, Yuan He, Masaaki Kondo:
DAISM: Digital Approximate In-SRAM Multiplier-Based Accelerator for DNN Training and Inference. 1-6 - Priyanjana Pal, Haibin Zhao, Maha Shatta, Michael Hefenbrock, Sina Bakhtavari Mamaghani, Sani R. Nassif, Michael Beigl, Mehdi B. Tahoori:
Analog Printed Spiking Neuromorphic Circuit. 1-6 - Joakim Lindén, Andreas Ermedahl, Hans Salomonsson, Masoud Daneshtalab, Björn Forsberg, Paris Carbone:
Autonomous Realization of Safety- and Time-Critical Embedded Artificial Intelligence. 1-4 - Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu:
BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network. 1-6 - Yoga Esa Wibowo, Cristian Cioflan, Thorir Mar Ingolfsson, Michael Hersche, Leo Zhao, Abbas Rahimi, Luca Benini:
12 mJ Per Class On-Device Online Few-Shot Class-Incremental Learning. 1-6 - Andrew Roberts, Mohammad Reza Heidari Iman, Mauro Bellone, Tara Ghasempouri, Jaan Raik, Olaf Maennel, Mohammad Hamad, Sebastian Steinhorst:
ADAssure: Debugging Methodology for Autonomous Driving Control Algorithms. 1-6 - Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang:
Heterogeneous Static Timing Analysis with Advanced Delay Calculator. 1-6 - George Antony, Gireesh Kumar K. M, Naiju Karim Abdul, Rahul M. Rao:
Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster Balancing. 1-2 - Xinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang, Jun Han:
RVCE-FAL: A RISC-V Scalar-Vector Custom Extension for Faster FALCON Digital Signature. 1-6 - Emanuele Parisi, Alberto Musa, Simone Manoni, Maicol Ciani, Davide Rossi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva:
TitanCFI: Toward Enforcing Control-Flow Integrity in the Root -of- Trust. 1-6 - Chenyu Tang, Chen Nie, Weikang Qian, Zhezhi He:
PIMLC: Logic Compiler for Bit-Serial Based PIM. 1-6 - Xianbin Li, Jiaqi Liu, Yuying Zhang, Yinyi Liu, Jiaxu Zhang, Chengeng Li, Shixi Chen, Yuxiang Fu, Fengshi Tian, Wei Zhang, Jiang Xu:
PhotonNTT: Energy-Efficient Parallel Photonic Number Theoretic Transform Accelerator. 1-6 - Ho-Jin Lee, Kyeong-Jun Lee, Youngchang Choi, Kyongsu Lee, Seokhyeong Kang, Jae-Yoon Sim:
Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation. 1-2 - Chunyun Chen, Lantian Li, Mohamed M. Sabry Aly:
ViTA: A Highly Efficient Dataflow and Architecture for Vision Transformers. 1-6 - Salma Afifi, Febin Sunny, Mahdi Nikdast, Sudeep Pasricha:
Accelerating Neural Networks for Large Language Models and Graph Processing with Silicon Photonics. 1-6 - João Paulo C. de Lima, Asif Ali Khan, Luigi Carro, Jerónimo Castrillón:
Full-Stack Optimization for CAM-Only DNN Inference. 1-6 - Chenguang Zhang, Zhihang Yuan, Xingchen Li, Guangyu Sun:
Algorithm-Hardware Co-Design for Energy-Efficient A/D Conversion in ReRAM-Based Accelerators. 1-6 - Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. 1-6 - Beatrice Alessandra Motetti, Luca Crupi, Mustafa Omer Mohammed Elamin Elshaigi, Matteo Risso, Daniele Jahier Pagliari, Daniele Palossi, Alessio Burrello:
Adaptive Deep Learning for Efficient Visual Pose Estimation Aboard Ultra-Low-Power Nano-Drones. 1-6 - Federico Nicolás Peccia, Alexander Viehl, Oliver Bringmann:
DIAPASON: Differentiable Allocation, Partitioning and Fusion of Neural Networks for Distributed Inference. 1-6 - Luca Colagrande, Luca Benini:
Optimizing Offload Performance in Heterogeneous MPSoCs. 1-2 - Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
Computational and Storage Efficient Quadratic Neurons for Deep Neural Networks. 1-6 - Zhao Yang, Shengbing Zhang, Chuxi Li, Haoyang Wang, Meng Zhang:
Resource-Efficient Heterogenous Federated Continual Learning on Edge. 1-6 - Filippo Muzzini, Nicola Capodieci, Roberto Cavicchioli, Benjamin Rouxel:
High-Performance Feature Extraction for GPU -Accelerated ORB-SLAMx. 1-2 - Vincent Meyers, Dennis Gnad, Mehdi Baradaran Tahoori:
Out-of-Distribution Detection Using Power-Side Channels for Improving Functional Safety of Neural Network FPGA Accelerators. 1-2 - Wei Tao, Shenglin He, Kai Lu, Xiaoyang Qu, Guokuan Li, Jiguang Wan, Jianzong Wang, Jing Xiao:
Value-Driven Mixed-Precision Quantization for Patch-Based Inference on Microcontrollers. 1-6 - Gerlando Sciangula, Daniel Casini, Alessandro Biondi, Claudio Scordino:
End-to-End Latency Optimization of Thread Chains Under the DDS Publish/Subscribe Middleware. 1-6 - Zikun Wei, Tingting Wang, Chenchen Ding, Bohan Wang, Ziyi Guan, Hantao Huang, Hao Yu:
FMTT: Fused Multi-Head Transformer with Tensor-Compression for 3D Point Clouds Detection on Edge Devices. 1-6 - Mahya Saffarpour, Kourosh Vali, Weitai Qian, Begum Kasap, Diana L. Farmer, Aijun Wang, Soheil Ghiasi:
Deep Quasi-Periodic Priors: Signal Separation in Wearable Systems with Limited Data. 1-2 - Kwondo Ma, Anurup Saha, Chandramouli N. Amarnath, Abhijit Chatterjee:
Learning Assisted Post-Manufacture Testing and Tuning of RRAM-Based DNNs for Yield Recovery. 1-6 - Hongquan He, Guowen Kuang, Qi Sun, Hao Geng:
PaLM: Point Cloud and Large Pre-trained Model Catch Mixed-type Wafer Defect Pattern Recognition. 1-6 - Michael Dominguez, Amin Rezaei:
CycPUF: Cyclic Physical Unclonable Function. 1-6 - Shengjie Zhou, Yongliang Chen, Xiaole Cui, Yun Liu:
Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUF. 1-6 - Maximilian Barger, Marco Brohet, Francesco Regazzoni:
Demonstrating Post-Quantum Remote Attestation for RISC-V Devices. 1-2 - Niraj Kumar, Chuanchao Gao, Arvind Easwaran:
Optimal Fixed Priority Scheduling in Multi-Stage Multi-Resource Distributed Real-Time Systems. 1-6 - Taha Shahroodi, Raphael Cardoso, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui:
High-Performance Data Mapping for BNNs on PCM-Based Integrated Photonics. 1-6 - Damien Chabrol, Guillaume Phavorin, Eric Jenn:
sLET for Distributed Aerospace Landing System. 1-2 - Elisavet Lydia Alvanaki, Manolis Katsaragakis, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris:
Decoupled Access-Execute Enabled DVFS for TinyML Deployments on STM32 Microcontrollers. 1-6 - Matteo Risso, Chen Xie, Francesco Daghero, Alessio Burrello, Seyedmorteza Mollaei, Marco Castellano, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari:
HW-SW Optimization of DNNs for Privacy-Preserving People Counting on Low-Resolution Infrared Arrays. 1-6 - Donghyun Lee, Ruokai Yin, Youngeun Kim, Abhishek Moitra, Yuhang Li, Priyadarshini Panda:
TT-SNN: Tensor Train Decomposition for Efficient Spiking Neural Network Training. 1-6 - Jiteshri Dasari, Maciej J. Ciesielski:
Combining Formal Verification and Testing for Debugging of Arithmetic Circuits. 1-6 - Huichuan Zheng, Mengying Zhao, Hao Zhang, Yuqing Xiong, Xiaojun Cai, Zhiping Jia:
Towards Efficient Reconfiguration through Lightweight Input Inversion for MLC NVFPGAs. 1-6 - Zexi Li, Haoran Jin, Kuncai Zhong, Guojie Luo, Runsheng Wang, Weikang Qian:
SCGen: A Versatile Generator Framework for Agile Design of Stochastic Circuits. 1-6 - Li Lu, Junchao Chen, Markus Ulbricht, Milos Krstic:
Towards SEU Fault Propagation Prediction with Spatio-Temporal Graph Convolutional Networks. 1-2 - Zishen Wan, Che-Kai Liu, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna, Arijit Raychowdhury:
H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations. 1-6 - Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler:
Dynamic Realization of Multiple Control Toffoli Gate. 1-6 - Veera Venkata Ram Murali Krishna Rao Muvva, Kunjan Theodore Joseph, Kruttidipta Samal, Marilyn Wolf, Santosh Pitla:
Adaptive Perception Control for Aerial Robots with Twin Delayed DDPG. 1-6 - Paul Delestrac, Debjyoti Bhattacharjee, Simei Yang, Diksha Moolchandani, Francky Catthoor, Lionel Torres, David Novo:
Multi-Level Analysis of GPU Utilization in ML Training Workloads. 1-6 - Levent Aksoy, Muhammad Yasin, Samuel Pagliarini:
KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking. 1-6 - Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù:
Scalable Sequential Optimization Under Observability Don't Cares. 1-6 - Dimitris Aspetakis, Leonidas Kosmidis, Matina Maria Trompouki, Jose Ruiz, Gábor Marosy:
Formal Methods for High Integrity GPU Software Development and Verification. 1-6 - Jimin Lee, Sangwoo Park, Junho Huh, Sanghyo Jeong, Inhwan Kim, Jae Min Kim:
I2SR: Immediate Interrupt Service Routine on RISC-V MCU to Control mmWave RF Transceivers. 1-2 - Hanyong Shao, Boyi Fu, Jinghao Yang, Wenpu Luo, Chang Su, Zhiyuan Fu, Kechao Tang, Ru Huang:
IMCE: An In-Memory Computing and Encrypting Hardware Architecture for Robust Edge Security. 1-6 - Pratyush Dhingra, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Ananth Kalyanaraman, Partha Pratim Pande:
FARe: Fault-Aware GNN Training on ReRAM-Based PIM Accelerators. 1-6 - Hao Zhang, Mengying Zhao, Huichuan Zheng, Yuqing Xiong, Yuhao Zhang, Zhaoyan Shen:
Towards High-Throughput Neural Network Inference with Computational BRAM on Nonvolatile FPGAs. 1-6 - Ayse K. Coskun, Fatih Acun, Quentin Clark, Can Hankendi, Daniel Curtis Wilson:
Data Center Demand Response for Sustainable Computing: Myth or Opportunity? 1-2 - Safin Bayes, Mohamed Hossam, Mohamed Hassan:
Shared Data Kills Real-Time Cache Analysis. How to Resurrect It? 1-6 - Dong Huang, Dan Feng, Qiankun Liu, Bo Ding, Wei Zhao, Xueliang Wei, Wei Tong:
A Read Latency Variation Aware Independent Read Scheme for QLC SSDs. 1-6 - Kisaru Liyanage, Hasindu Gamaarachchi, Hassaan Saadat, Tuo Li, Hiruna Samarakoon, Sri Parameswaran:
Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions. 1-6 - Aruna Jayasena, Richard Bachmann, Prabhat Mishra:
EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves. 1-6 - Ruixuan Wang, Wengying Wen, Kyle Juretus, Xun Jiao:
PP-HDC: A Privacy-Preserving Inference Framework for Hyperdimensional Computing. 1-6 - Onat Güngör, Tajana Rosing, Baris Aksanli:
ROLDEF: RObust Layered DEFense for Intrusion Detection Against Adversarial Attacks. 1-6 - Aron Harder, Madhur Behl:
Automated Traffic Scenario Description Extraction Using Video Transformers. 1-6 - Wenxue Wu, Zhen Li, Tong Zhang, Xiaoqin Feng, Liwei Zhang, Xuelong Qi, Fengyuan Ren:
Dynamic Per-Flow Queues for TSN Switches. 1-2 - Mertcan Temel:
Formal Verification of Booth Radix-8 and Radix-16 Multipliers. 1-6 - Qingrong Huang, Hamza Errahmouni Barkam, Zeyu Yang, Jianyi Yang, Thomas Kämpfe, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Mohsen Imani, Cheng Zhuo, Xunzhao Yin:
A FeFET-based Time-Domain Associative Memory for Multi-bit Similarity Computation. 1-6 - Jiang Li, Yijun Cui, Chenghua Wang, Weiqiang Liu, Shahar Kvatinsky:
A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing. 1-6 - Sercan Aygun, Mehran Shoushtari Moghadam, M. Hassan Najafi:
uHD: Unary Processing for Lightweight and Dynamic Hyperdimensional Computing. 1-6 - Khalil Esper, Stefan Wildermann, Jürgen Teich:
Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. 1-2 - Satoshi Kawakami, Yusuke Ohtusbo, Koji Inoue, Masamitsu Tanaka:
Late Breaking Results: Single Flux Quantum Based Brownian Circuits for Ultra-Law-Power Computing. 1-2 - Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, Maya B. Gokhale:
Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine. 1-2 - Jiahang Lou, Xuchen Gao, Yiqing Mao, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang:
An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture. 1-6 - Jinkyu Yim, Jaeyong Song, Yerim Choi, Jaebeen Lee, Jaewon Jung, Hongsun Jang, Jinho Lee:
Pipette: Automatic Fine-Grained Large Language Model Training Configurator for Real-World Clusters. 1-6 - Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini:
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. 1-6 - Ziyi Guan, Boyu Li, Yuan Ren, Muqun Niu, Hantao Huang, Graziano Chesi, Hao Yu, Ngai Wong:
An Isotropic Shift-Pointwise Network for Crossbar-Efficient Neural Network Design. 1-6 - Simon Toni Hofmann, Marcel Walter, Robert Wille:
MNT Bench: Benchmarking Software and Layout Libraries for Field-Coupled Nanocomputing. 1-2 - Josu Oca, Montserrat Hermo, Alexander Bolotov:
A Sound and Complete Algorithm to Identify Independent Variables in a Reactive System Specification. 1-2 - Yuanyuan Duan, Xingchen Liu, Zhiping Yu, Hanming Wu, Leilai Shao, Xiaolei Zhu:
RLPlanner: Reinforcement Learning Based Floorplanning for Chiplets with Fast Thermal Analysis. 1-2 - Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang:
ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. 1-6 - Chenyi Wen, Haonan Du, Zhengrui Chen, Li Zhang, Qi Sun, Cheng Zhuo:
PACE: A Piece-Wise Approximate and Configurable Floating - Point Divider for Energy - Efficient Computing. 1-6 - Sunan Zou, Jiaxi Zhang, Bizhao Shi, Guojie Luo:
BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call. 1-6 - Ranyang Zhou, Sabbir Ahmed, Arman Roohi, Adnan Siraj Rakin, Shaahin Angizi:
DRAM-Locker: A General-Purpose DRAM Protection Mechanism Against Adversarial DNN Weight Attacks. 1-6 - Mohamed Ibrahim, Youbin Kim, Jan M. Rabaey:
Efficient Design of a Hyperdimensional Processing Unit for Multi-Layer Cognition. 1-6 - Tousif Rahman, Gang Mao, Sidharth Maheshwari, Rishad A. Shafik, Alex Yakovlev:
MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications. 1-6 - Jianfeng Wang, Shuwen Deng, Huazhong Yang, Vijaykrishnan Narayanan, Xueqing Li:
TroScan: Enhancing On-Chip Delivery Resilience to Physical Attack Through Frequency-Triggered Key Generation. 1-6 - Sumukh Pinge, Weihong Xu, Jaeyoung Kang, Tianqi Zhang, Niema Moshiri, Wout Bittremieux, Tajana Rosing:
SpecHD: Hyperdimensional Computing Framework for FPGA-Based Mass Spectrometry Clustering. 1-6 - Siyi Huang, Yajuan Du, Yi Fan, Cheng Ji:
Extending SSD Lifetime via Balancing Layer Endurance in 3D NAND Flash Memory. 1-2 - Khaled Sidahmed Sidahmed Alamin, Davide Appello, Alessandro Beghi, Nicola Dall'Ora, Fabio Depaoli, Santa Di Cataldo, Franco Fummi, Sebastiano Gaiardelli, Michele Lora, Enrico Macii, Alessio Mascolini, Daniele Pagano, Francesco Ponzio, Gian Antonio Susto, Sara Vinco:
An AI-Enabled Framework for Smart Semiconductor Manufacturing. 1-6 - Alberto Ancilotto, Francesco Paissan, Elisabetta Farella:
XiNet-pose: Extremely Lightweight Pose Detection for Microcontrollers. 1-6 - Matthias Stammler, Julian Lorenz, Eric Sax, Jürgen Becker, Matthias Hamann, Patrick Bidinger, Andreas Dewald, Paraskevi Georgouti, Alexios Camarinopoulos, Günter Becker, Klaus Finsterbusch, Maximilian Kirschner, Laurenz Adolph, Carl Philipp Hohl, Maria Rill, Daniel Vonderau, Victor Pazmino Betancourt:
UNCOVER: Data-Driven Design Support through Continuous Monitoring of Security Incidents. 1-6 - Tsung-Yu Liu, Yen An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng:
ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. 1-2 - Haotian Xu, Jianyi Yang, Cheng Zhuo, Thomas Kämpfe, Kai Ni, Xunzhao Yin:
Reconfigurable Frequency Multipliers Based on Complementary Ferroelectric Transistors. 1-6 - Daniel Bochen Tan, Shuohao Ping, Jason Cong:
Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization. 1-6 - Jaemin Seo, Sejin Park, Seokhyeong Kang:
Unveiling the Black-Box: Leveraging Explainable AI for FPGA Design Space Optimization. 1-6 - Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han:
GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. 1-6 - Jing Gong, Hassaan Saadat, Haris Javaid, Hasindu Gamaarachchi, David Taubman, Sri Parameswaran:
SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators. 1-6 - Yushu Wu, Chao Wu, Geng Yuan, Yanyu Li, Weichao Guo, Jing Rao, Xipeng Shen, Bin Ren, Yanzhi Wang:
DACO: Pursuing Ultra-low Power Consumption via DNN-Adaptive CPU-GPU CO-optimization on Mobile Devices. 1-2 - Xinyu Wang, Xiaotian Sun, Yinhe Han, Xiaoming Chen:
PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators. 1-2 - Giorgos Armeniakos, Paula L. Duarte, Priyanjana Pal, Georgios Zervakis, Mehdi B. Tahoori, Dimitrios Soudris:
On-Sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design. 1-6 - Hanzhi Xun, Moritz Fieback, Sicong Yuan, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui:
Device-Aware Diagnosis for Yield Learning in RRAMs. 1-6 - Tanja Harbaum, Alexey Serdyuk, Fabian Kreß, Tim Hamann, Jens Barth, Peter Kämpf, Florent Imbert, Yann Soullard, Romain Tavenard, Éric Anquetil, Jessica Delahaie:
KIHT: Kaligo-Based Intelligent Handwriting Teacher. 1-6 - Moritz Scherer, Cristian Cioflan, Michele Magno, Luca Benini:
Work in Progress: Linear Transformers for TinyML. 1-2 - Tim Henkes, Steffen Reith, Marc Stöttinger, Norbert Herfurth, Goran Panic, Julian Wälde, Fabian Buschkowski, Pascal Sasdrich, Christoph Lüth, Milan Funck, Tuba Kiyan, Arnd Weber, Detlef Boeck, René Rathfelder, Torsten Grawunder:
Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP. 1-6 - Tianchen Gu, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, Xuan Zeng:
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling. 1-6 - Souradip Poddar, Ahmet Faruk Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia, David Z. Pan:
A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing. 1-6 - Harsh Sharma, Gaurav Narang, Janardhan Rao Doppa, Ümit Y. Ogras, Partha Pratim Pande:
Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads. 1-6 - Omais Pandith, Rafail Psiakis, Johanna Toivanen:
EMAClave: An Efficient Memory Authentication for RISCV Enclaves. 1-6 - Chathura Rajapaksha, Leila Delshadtehrani, Richard Muri, Manuel Egele, Ajay Joshi:
IOMMU Deferred Invalidation Vulnerability: Exploit and Defense. 1-6 - Lunshuai Pan, Pushen Zuo, Yubiao Luo, Zhong Sun, Ru Huang:
BlockAMC: Scalable In-Memory Analog Matrix Computing for Solving Linear Systems. 1-6 - Shengwen Liang, Ziming Yuan, Ying Wang, Dawen Xu, Huawei Li, Xiaowei Li:
HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System. 1-6 - Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim:
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. 1-6 - Omar Sharif, Christos-Savvas Bouganis:
A Framework for Designing Scalable Gaussian Belief Propagation Accelerators for use in SLAM. 1-2 - Siyan Chen, Rongliang Fu, Junying Huang, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan:
JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. 1-6 - Zijun Jiang, Yangdi Lyu:
Microprocessor Design Space Exploration via Space Partitioning and Bayesian Optimization. 1-2 - Zhicheng Xu, Che-Kai Liu, Chao Li, Ruibin Mao, Jianyi Yang, Thomas Kämpfe, Mohsen Imani, Can Li, Cheng Zhuo, Xunzhao Yin:
FeReX: A Reconfigurable Design of Multi-Bit Ferroelectric Compute-in-Memory for Nearest Neighbor Search. 1-6 - Hongyi Zhang, Haozhe Zhu, Siqi He, Mengjie Li, Chengchen Wang, Xiankui Xiong, Haidong Tian, Xiaoyang Zeng, Chixiao Chen:
ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. 1-6 - Yanjie Zhen, Weining Chen, Wei Gao, Ju Ren, Kang Chen, Yu Chen:
Intelligent Hybrid Memory Scheduling Based on Page Pattern Recognition. 1-2 - Hyunsei Lee, Hyukjun Kwon, Jiseung Kim, Seohyun Kim, Mohsen Imani, Yeseong Kim:
Towards Forward-Only Learning for Hyperdimensional Computing. 1-2 - Jiahao Sun, Fangxin Liu, Yijian Zhang, Li Jiang, Rui Yang:
RTSA: An RRAM-TCAM based In-Memory-Search Accelerator for Sub-100 µs Collision Detection. 1-2 - Amir Fakhim Babaei, Thidapat Chantem:
SGPRS: Seamless GPU Partitioning Real-Time Scheduler for Periodic Deep Learning Workloads. 1-2 - Sourav Das, Aritra Hazra, Pallab Dasgupta, Sudipta Kundu, Himanshu Jain:
PURSE: Property Ordering Using Runtime Statistics for Efficient Multi - Property Verification. 1-6 - Filip Sabo, Aida Todri-Sanial:
ClassONN: Classification with Oscillatory Neural Networks Using the Kuramoto Model. 1-2 - Mirco De Marchi, Nicola Bombieri:
Orchestration-Aware Optimization of ROS2 Communication Protocols. 1-6 - Federico Gavioli, Gianluca Brilli, Paolo Burgio, Davide Bertozzi:
Adaptive Localization for Autonomous Racing Vehicles with Resource-Constrained Embedded Platforms. 1-6 - Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang:
AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction. 1-2 - Rassul Bairamkulov, Mingfei Yu, Giovanni De Micheli:
Unleashing the Power of T1-Cells in SFQ Arithmetic Circuits. 1-2 - Sunyoung Park, Hyunji Kim, Hana Kim, Ji-Hoon Kim:
PA-2SBF: Pattern-Adaptive Two-Stage Bloom Filter for Run-Time Memory Diagnostic Data Compression in Automotive SoCs. 1-6 - Yingjie Li, Anthony Agnesina, Yanqing Zhang, Haoxing Ren, Cunxi Yu:
BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation. 1-2 - Giuseppe Stracquadanio, Sourav Medya, Stefano Quer, Debjit Pal:
VeriBug: An Attention-Based Framework for Bug Localization in Hardware Designs. 1-2 - Matteo Antonio Scrugli, Paola Busia, Gianluca Leone, Paolo Meloni:
On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis. 1-6 - Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler:
LLM-Guided Formal Verification Coupled with Mutation Testing. 1-2 - Vasudev Gohil, Rahul Kande, Chen Chen, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran:
MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors. 1-6 - Yuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng:
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. 1-2 - Jian Shi, Wenjing Zhang, Weikang Qian:
CLAST: Cross-Layer Approximate High-Level Synthesis with Configurable Approximate Three-Operand Adders. 1-2 - Paul R. Genssler, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch:
HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit Recognition. 1-2 - Jingyu Jia, Jianwang Zhai, Kang Zhao:
Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model. 1-2 - Liwei Zhang, Tong Zhang, Wenxue Wu, Xiaoqin Feng, Guoxi Lin, Fengyuan Ren:
Fault- Tolerant Cyclic Queuing and Forwarding in Time-Sensitive Networking. 1-6 - Chao Xiao, Yifei Deng, Zhijie Yang, Renzhi Chen, Hong Wang, Jingyue Zhao, Huadong Dai, Lei Wang, Yuhua Tang, Weixia Xu:
LLM-Based Processor Verification: A Case Study for Neuronnorphic Processor. 1-6 - Zamshed I. Chowdhury, Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
On Gate Flip Errors in Computing-In-Memory. 1-6 - Chang Meng, Hanyu Wang, Yuqi Mai, Weikang Qian, Giovanni De Micheli:
VACSEM: Verifying Average Errors in Approximate Circuits Using Simulation-Enhanced Model Counting. 1-6 - Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler:
Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. 1-6 - Xiaojun Cai, Nanxiang Yu, Mengying Zhao, Mei Cao, Tingting Zhang, Jianbo Lu:
Decentralized Federated Learning in Partially Connected Networks with Non-IID Data. 1-6 - Quanling Zhao, Xiaofan Yu, Shengfan Hu, Tajana Rosing:
MultimodalHD: Federated Learning Over Heterogeneous Sensor Modalities using Hyperdimensional Computing. 1-6 - Hucheng Liu, Shaohuai Shi, Xuan Wang, Zoe L. Jiang, Qian Chen:
Performance Analysis and Optimizations of Matrix Multiplications on ARMv8 Processors. 1-6 - Yichao Dong, Dan Niu, Zhou Jin, Chuan Zhang, Changyin Sun, Zhenya Zhou:
ISPT-Net: A Noval Transient Backward-Stepping Reduction Policy by Irregular Sequential Prediction Transformer. 1-6 - Yanyue Xie, Peiyan Dong, Geng Yuan, Zhengang Li, Masoud Zabihi, Chao Wu, Sung-En Chang, Xufeng Zhang, Xue Lin, Caiwen Ding, Nobuyuki Yoshikawa, Olivia Chen, Yanzhi Wang:
SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum- Flux - Parametron Superconducting Circuits. 1-6 - Pierpaolo Morì, Moritz Thoma, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone:
MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting. 1-6 - Alessandro Tempia Calvino, Giovanni De Micheli:
Scalable Logic Rewriting Using Don't Cares. 1-6 - Konstantina Koliogeorgi, George Anagnostopoulos, Gerardo Zampino, Marcial Sanchis, Ricardo Vinuesa, Sotirios Xydis:
Auto-tuning Multi-GPU High-Fidelity Numerical Simulations for Urban Air Mobility. 1-6 - Stefano Mercogliano, Daniele Ottaviano, Alessandro Cilardo, Marcello Cinque:
Lightweight and Predictable Memory Virtualization on Medium-Size Microcontrollers. 1-2 - Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Hidden Cost of Circuit Design with RFETs. 1-2 - Longfei Luo, Han Wang, Dingcui Yu, Yina Lv, Liang Shi:
CPF: A Cross-Layer Prefetching Framework for High-Density Flash-Based Storage. 1-6 - Framcisco Herrera:
Responsible Artificial Intelligence Systems: From Trustworthiness to Governance. 1-2 - Paul R. Genssler, Sandy A. Wasif, Miran Wael, Rodion Novkin, Hussam Amrouch:
Frontiers in Edge AI with RISC-V: Hyperdimensional Computing vs. Quantized Neural Networks. 1-6 - Mattia Gerardi, Arvind Sharma, Yang Xiang, Jakub Kaczmarek, Fernando García-Redondo, Maarten Rosmeulen, Marie Garcia Bardon:
A DTCO Framework for 3D NAND Flash Readout. 1-2 - Taixin Li, Hongtao Zhong, Juejian Wu, Thomas Kämpfe, Kai Ni, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li:
CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging. 1-6 - Heba Khdr, Mustafa Enes Batur, Kanran Zhou, Mohammed Bakr Sikal, Jörg Henkel:
Multi-Agent Reinforcement Learning for Thermally-Restricted Performance Optimization on Manycores. 1-6 - Niladri Bhattacharjee, Viktor Havel, Suruchi Kumari, Nima Kavand, Jorge Navarro Quijada, Akash Kumar, Thomas Mikolajick, Jens Trommer:
Dynamic Reconfigurable Security Cells Based on Emerging Devices Integrable in FDSOI Technology. 1-6 - Tian Yi Lim, Edoardo Ghignone, Nicolas Baumann, Michele Magno:
Robustness Evaluation of Localization Techniques for Autonomous Racing. 1-2 - Danish Gufran, Sudeep Pasricha:
CALLOC: Curriculum Adversarial Learning for Secure and Robust Indoor Localization. 1-6 - Luke Vassallo, Josef Bajada:
Learning Circuit Placement Techniques Through Reinforcement Learning with Adaptive Rewards. 1-6 - Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. 1-6 - Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. 1-6 - Sadaf Khan, Zhengyuan Shi, Min Li, Qiang Xu:
DeepSeq: Deep Sequential Circuit Learning. 1-2 - Gideon Mohr, Marco Guarnieri, Jan Reineke:
Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors. 1-6 - Trishna Rajkumar, Johnny Öberg:
Guided Fault Injection Strategy for Rapid Critical Bit Detection in Radiation-Prone SRAM-FPGA. 1-6 - Sosei Ikeda, Hiromitsu Awano, Takashi Sato:
Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent. 1-6 - Thilo L. Fischer, Heiko Falk:
Shared Cache Analysis Under Preemptive Scheduling. 1-6 - Hazem Abaza, Debayan Roy, Shiqing Fan, Selma Saidi, Antonios Motakis:
Trace-Enabled Timing Model Synthesis for ROS2-based Autonomous Applications. 1-6 - Tom Glint, Mithil Pechimuthu, Joycee Mekie:
DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators. 1-6 - Mai Al-Zu'bi, Georg Weissenbacher:
Statistical Profiling of Micro-Architectural Traces and Machine Learning for Spectre Detection: A Systematic Evaluation. 1-6 - Han Wang, Ming Tang, Ke Xu, Quancheng Wang:
Cache Bandwidth Contention Leaks Secrets. 1-6 - Dongjoon Lee, Jongin Choe, Chanyoung Park, Kyungtae Kang, Mahmut T. Kandemir, Wonil Choi:
An Autonomic Resource Allocating SSD. 1-6 - Roberto Bosio, Giovanni Brignone, Filippo Minnella, M. Usman Jamal, Luciano Lavagno:
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. 1-2 - Robert Wille:
Design Automation for Quantum Computing: Intermediate Stage Report of the ERC Consolidator Grant "DAQC". 1-6 - Xing Huang, Jiaxuan Wang, Zhiwen Yu, Bin Guo, Tsung-Yi Ho, Ulf Schlichtmann, Krishnendu Chakrabarty:
PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip Systems. 1-6 - Chengeng Li, Fan Jiang, Shixi Chen, Xianbin Li, Jiaqi Liu, Wei Zhang, Jiang Xu:
Towards Scalable GPU System with Silicon Photonic Chiplet. 1-6 - Mohammad Reza Heidari Iman, Gert Jervan, Tara Ghasempouri:
ARTmine: Automatic Association Rule Mining with Temporal Behavior for Hardware Verification. 1-6 - Xiaotian Zhao, Tianju Wang, Run Jiao, Xinfei Guo:
Standard Cells Do Matter: Uncovering Hidden Connections for High-Quality Macro Placement. 1-6 - Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne:
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving. 1-6 - Zheng Wu, Xiaoling Yi, Li Shang, Fan Yang:
SenseDSE: Sensitivity-Based Performance Evaluation for Design Space Exploration of Microarchitecture. 1-6 - Danny Abraham, Biswadip Maity, Bryan Donyanavard, Nikil D. Dutt:
Back to the Future: Reversible Runtime Neural Network Pruning for Safe Autonomous Systems. 1-6 - Muhammad Kashif, Muhammad Rashid, Saif Al-Kuwari, Muhammad Akmal Shafique:
Alleviating Barren Plateaus in Parameterized Quantum Machine Learning Circuits: Investigating Advanced Parameter Initialization Strategies. 1-6 - Yi Guo, Qilin Zhou, Xiu Chen, Heming Sun:
High-Efficiency FPGA - Based Approximate Multipliers with LUT Sharing and Carry Switching. 1-2 - Marcel Walter, Jeremiah Croshaw, Samuel Sze Hang Ng, Konrad Walus, Robert A. Wolkow, Robert Wille:
Towards Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H -Si $(100)-2\times 1$ Surface. 1-2 - Xueyuan Liu, Zhuoran Song, Xiang Liao, Xing Li, Tao Yang, Fangxin Liu, Xiaoyao Liang:
Sava: A Spatial- and Value-Aware Accelerator for Point Cloud Transformer. 1-6 - Yehuda Kra, Naama Kra, Adam Teman:
Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors. 1-6 - Carmen G. Almudéver, Robert Wille, Fabio Sebastiano, Nadia Haider, Eduard Alarcón:
From Designing Quantum Processors to Large-Scale Quantum Computing Systems. 1-10 - Bing Li, Wendi Sun, Xiaobing Ni, Kaixuan He, Qi Xu, Song Chen, Yi Kang:
Parallel Multi-Objective Bayesian Optimization Framework for CGRA Microarchitecture. 1-6 - Binjie Yan, Lin Xu, Zefang Yu, Mingye Xie, Wei Ran, Jingsheng Gao, Yuzhuo Fu, Ting Liu:
Learning to Floorplan like Human Experts via Reinforcement Learning. 1-2 - Edward Manca, Luca Urbinati, Mario R. Casu:
STAR: Sum-Together/Apart Reconfigurable Multipliers for Precision-Scalable ML Workloads. 1-6 - Xingyue Qian, Zhezhi He, Weikang Qian:
An Efficient Logic Operation Scheduler for Minimizing Memory Footprint of In-Memory SIMD Computation. 1-2 - William H. Widen, Marilyn Claire Wolf:
Corporate Governance and Management of AI-Driven Product Development: Vehicle Automation. 1-6 - Giuseppe Chiari, Davide Galli, Francesco Lattari, Matteo Matteucci, Davide Zoni:
A Deep- Learning Technique to Locate Cryptographic Operations in Side-Channel Traces. 1-6 - Mathieu Toubeix, Eric Guthmuller, Adrian Evans, Tristan Meunier:
A Scalable Low-Latency FPGA Architecture for Spin Qubit Control Through Direct Digital Synthesis. 1-2 - Zhangying He, Chelsea William Fernandes, Hossein Sayadi:
ObfusGate: Representation Learning-Based Gatekeeper for Hardware-Level Obfuscated Malware Detection. 1-2 - Xingyu Mo, Yawen Li, Dajiang Liu:
Optimizing Imperfectly-Nested Loop Mapping on CGRAs via Polyhedral-Guided Flattening. 1-6 - Mohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi:
Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing. 1-6 - Xinkuang Geng, Siting Liu, Jianfei Jiang, Kai Jiang, Honglan Jiang:
Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks. 1-6 - Ruidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li:
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation. 1-6 - Shuaiwen Yu, Zhibing Sha, Chengyong Tang, Zhigang Cai, Peng Tang, Min Huang, Jun Li, Jianwei Liao:
Adaptive DRAM Cache Division for Computational Solid-state Drives. 1-6 - Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. 1-6 - Artem Klashtorny, Mahesh Tripunitara, Hiren D. Patel:
A Compiler Phase to Optimally Split GPU Wavefronts for Safety-Critical Systems. 1-6 - Hanqiu Wang, Max Panoff, Zihao Zhan, Shuo Wang, Christophe Bobda, Domenic Forte:
Programmable EM Sensor Array for Golden-Model Free Run-Time Trojan Detection and Localization. 1-6 - Manfred Schlägl, Moritz Stockinger, Daniel Große:
A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level. 1-6 - Florentia Afentaki, Michael Hefenbrock, Georgios Zervakis, Mehdi B. Tahoori:
Embedding Hardware Approximations in Discrete Genetic-Based Training for Printed MLPs. 1-6 - Nael Mizanur Rahman, Uday Kamal, Manish Nagaraj, Shaunak Roy, Saibal Mukhopadhyay:
Driving Autonomy with Event-Based Cameras: Algorithm and Hardware Perspectives. 1-6 - Christian Hakert, Kuan-Hsun Chen, Jian-Jia Chen:
FLInt: Exploiting Floating Point Enabled Integer Arithmetic for Efficient Random Forest Inference. 1-2 - Jaeyoung Kang, You Hak Lee, Minxuan Zhou, Weihong Xu, Tajana Rosing:
HygHD: Hyperdimensional Hypergraph Learning. 1-6 - Benjamin Carrion Schafer, Chaitali G. Sathe:
Circumventing Restrictions in Commercial High-Level Synthesis Tools. 1-2 - Andrew B. Kahng, Seokhyeong Kang, Minhyuk Kweon:
Improvement of Mixed Track - Height Standard-Cell Placement. 1-6 - Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang:
CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning. 1-6 - Haoyuan Li, Dingcheng Yang, Wenjian Yu:
Training Better CNN Models for 3-D Capacitance Extraction with Neural Architecture Search. 1-2 - Bharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb:
Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes. 1-6 - Nasr-Eddine Ouldei Tebina, Luc Salvo, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri:
Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification. 1-6 - Omid Bazangani, Parisa Amiri-Eliasi, Stjepan Picek, Lejla Batina:
Can Machine Learn Pipeline Leakage? 1-6 - Tuo Dai, Bizhao Shi, Guojie Luo:
WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on ACAP. 1-6 - Fabio Pavanello, Cédric Marchand, Paul Jiménez, Xavier Letartre, Ricardo Chaves, Niccolò Marastoni, Alberto Lovato, Mariano Ceccato, George Papadimitriou, Vasileios Karakostas, Dimitris Gizopoulos, Roberta Bardini, Tzamn Melendez Carmona, Stefano Di Carlo, Alessandro Savino, Laurence Lerch, Ulrich Rührmair, Sergio Vinagrero Gutierrez, Giorgio Di Natale, Elena Ioana Vatajelu:
Security Layers and Related Services within the Horizon Europe NEUROPULS Project. 1-6 - Daniel Große, Lucas Klemmer, Dominik Bonora:
Using Formal Verification Methods for Optimization of Circuits Under External Constraints. 1-6 - Jingyu He, Fengbin Tu, Kwang-Ting Cheng, Chi-Ying Tsui:
AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive Posit. 1-2 - Pengju Chen, Dan Niu, Zhou Jin, Changyin Sun, Qi Li, Hao Yan:
TSA-TICER: A Two-Stage TICER Acceleration Framework for Model Order Reduction. 1-6 - Qingcai Jiang, Shaojie Tan, Junshi Chen, Hong An:
A3PIM: An Automated, Analytic and Accurate Processing-in-Memory Offloader. 1-6 - Hamidreza Alikhani, Ziyu Wang, Anil Kanduri, Pasi Liljeberg, Amir M. Rahmani, Nikil D. Dutt:
SEAL: Sensing Efficient Active Learning on Wearables through Context-awareness. 1-2 - Youngmin Oh, Doyun Kim, Yoon Hyeok Lee, Bosun Hwang:
CRONuS: Circuit Rapid Optimization with Neural Simulator. 1-6 - Ruiqi Sun, Yinchen Ni, Xin He, Jie Zhao, An Zou:
ONE-SA: Enabling Nonlinear Operations in Systolic Arrays For Efficient and Flexible Neural Network Inference. 1-6 - Tobias Dörr, Florian Schade, Jürgen Becker, Georgios Keramidas, Nikos Petrellis, Vasilios I. Kelefouras, Michail Mavropoulos, Konstantinos Antonopoulos, Christos P. Antonopoulos, Nikolaos S. Voros, Alexander Ahlbrecht, Wanja Zaeske, Vincent Janson, Phillip Nöldeke, Umut Durak, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Clemens Reichmann, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Wolfgang Gabler, Katrin Weiden, Xavier Anzuela Recasens, Sakir Sezer, Fahad Siddiqui, Rafiullah Khan, Kieran McLaughlin, Sena Yengec Tasdemir, Balmukund Sonigara, Henry Hui, Esther Soriano Viguer, Aridane Álvarez Suárez, Vicente Nicolau Gallego, Manuel Muñoz Alcobendas, Miguel Masmano Tello:
XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software Systems. 1-6 - Benzheng Li, Hailong You, Shunyang Bi, Yuming Zhang:
An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints. 1-6 - Seunggyu Lee, Daijoon Hyun, Younggwang Jung, Gangmin Cho, Youngsoo Shin:
Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model. 1-6 - Alejandro J. Calderón, Irune Yarza, Stefano Sinisi, Lorenzo Lazzara, Valerio Di Valerio, Giulia Stazi, Leonidas Kosmidis, Matina Maria Trompouki, Alessandro Ulisse, Aitor Amonarriz, Peio Onaindia:
The METASAT Model-Based Engineering Workflow and Digital Twin Concept. 1-6 - Seyedeh Maryam Ghasemi, Sergej Meschkov, Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori:
In-Field Detection of Small Delay Defects and Runtime Degradation Using On-Chip Sensors. 1-2 - Markus Krausz, Jan Philipp Thoma, Florian Stolz, Marc Fyrbiak, Tim Güneysu:
Three Sidekicks to Support Spectre Countermeasures. 1-6 - Michele Lora, Sebastiano Gaiardelli, Chanwook Oh, Stefano Spellini, Pierluigi Nuzzo, Franco Fummi:
Design Automation for Cyber-Physical Production Systems: Lessons Learned from the DeFacto Project. 1-6 - Mahboobe Sadeghipour Roodsari, Jonas Krautter, Mehdi B. Tahoori:
OTFGEncoder - HDC: Hardware-efficient Encoding Techniques for Hyperdimensional Computing. 1-2 - Wenye Liu, Nazim Altar Koca, Chip-Hong Chang:
Efficient Fast Additive Homomorphic Encryption Cryptoprocessor for Privacy-Preserving Federated Learning Aggregation. 1-6 - Tobias Strauch:
Deductive Formal Verification of Synthesizable, Transaction-Level Hardware Designs Using Coq. 1-6 - Nima Kavand, Armin Darjani, Giulio Galderisi, Jens Trommer, Thomas Mikolajick, Akash Kumar:
REDCAP: Reconfigurable RFET-Based Circuits Against Power Side-Channel Attacks. 1-6 - Sami Ben Ali, Silviu-Ioan Filip, Olivier Sentieys:
A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training. 1-6 - Yuta Shintani, Michiko Inoue, Michihiro Shintani:
Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process. 1-6 - Hanyu Wang, Jason Cong, Giovanni De Micheli:
Quantum State Preparation Using an Exact CNOT Synthesis Formulation. 1-6 - Rassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Giovanni De Micheli:
Technology-Aware Logic Synthesis for Superconducting Electronics. 1-6 - Michael T. Niemier, Z. Enciso, M. Sharifi, Xiaobo Sharon Hu, Ian O'Connor, A. Graening, R. Sharma, P. Gupta, Jerónimo Castrillón, João Paulo C. de Lima, Asif Ali Khan, H. Farzaneh, N. Afroze, Asif Khan, Julien Ryckaert:
Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers. 1-10 - Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer:
EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. 1-6 - Edward A. Lee:
Certainty or Intelligence: Pick One! 1-2 - Ye Qiao, Haocheng Xu, Yifan Zhang, Sitao Huang:
MicroNAS: Zero-Shot Neural Architecture Search for MCUs. 1-2 - Lixia Han, Peng Huang, Zheng Zhou, Yiyang Chen, Haozhang Yang, Xiaoyan Liu, Jinfeng Kang:
Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference Accelerators. 1-2 - Bo Yang, Qi Xu, Hao Geng, Song Chen, Yi Kang:
Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner. 1-6 - Francesco Regazzoni, Gergely Ács, Albert Zoltan Aszalos, Christos Avgerinos, Nikolaos Bakalos, Josep Lluis Berral, Joppe W. Bos, Marco Brohet, Andrés G. Castillo Sanz, Gareth T. Davies, Stefanos Florescu, Pierre-Elisée Flory, Alberto Gutierrez-Torre, Evangelos Haleplidis, Alice Héliou, Sotirios Ioannidis, Alexander Islam El-Kady, Katarzyna Kapusta, Konstantina Karagianni, Pieter Kruizinga, Kyrian Maat, Zoltán Ádám Mann, Kalliopi Mastoraki, SeoJeong Moon, Maja Nisevic, Balázs Pejó, Kostas Papagiannopoulos, Vassilis Paliouras, Paolo Palmieri, Francesca Palumbo, Juan Carlos Pérez Baun, Péter Pollner, Eduard Porta-Pardo, Luca Pulina, Muhammad Ali Siddiqi, Daniela Spajic, Christos Strydis, Georgios Tasopoulos, Vincent Thouvenot, Christos Tselios, Apostolos P. Fournaris:
SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data Space. 1-4 - Eduardo Chielle, Oleg Mazonka, Michail Maniatakos:
Optimizing Ciphertext Management for Faster Fully Homomorphic Encryption Computation. 1-6 - Younghyun Lee, Hyejun Kim, Yongseung Yu, Myeongjin Cho, Jiwon Seo, Yongjun Park:
Discovering Efficient Fused Layer Configurations for Executing Multi-Workloads on Multi-Core NPUs. 1-6 - Supriyo Maji, Sungyoung Lee, David Z. Pan:
Analog Transistor Placement Optimization Considering Nonlinear Spatial Variations. 1-6 - Fatemeh Ghasemi, Lukas Liedtke, Magnus Jahre:
ECM: Improving IoT Throughput with Energy-Aware Connection Management. 1-6 - Davy Million, Noelia Oliete-Escuín, César Fuguet:
Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache. 1-2 - Seungmin Woo, Hyunsoo Lee, Yunjeong Shin, MinSeok Han, Yunjeong Go, Jongbeom Kim, Hyundong Lee, Hyunwoo Kim, Taigon Song:
Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction. 1-6 - Xiaolu Hu, Ao Liu, Xinkuang Geng, Zizhong Wei, Kai Jiang, Honglan Jiang:
A Configurable Approximate Multiplier for CNNs Using Partial Product Speculation. 1-6 - Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang:
A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. 1-6 - Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, Taewhan Kim:
BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost. 1-6 - Yunfan Zuo, Yuyang Ye, Hongchao Zhang, Tinghuan Chen, Hao Yan, Longxing Shi:
A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects. 1-6 - Xueyuan Liu, Zhuoran Song, Guohao Dai, Gang Li, Can Xiao, Yan Xiang, Dehui Kong, Ke Xu, Xiaoyao Liang:
FusionArch: A Fusion-Based Accelerator for Point-Based Point Cloud Neural Networks. 1-6 - Hongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang, Fan Yang, Xuan Zeng, Zhufei Chu:
A Semi-Tensor Product based Circuit Simulation for SAT-sweeping. 1-6 - Najmeh Nazari, Behnam Omidi, Chongzhou Fang, Hosein Mohammadi Makrani, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, Khaled N. Khasawneh:
SpecScope: Automating Discovery of Exploitable Spectre Gadgets on Black-Box Microarchitectures. 1-6 - Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, Bei Yu:
CBTune: Contextual Bandit Tuning for Logic Synthesis. 1-6 - Ruiyang Ma, Huatao Zhao, Jiayi Huang, Shijian Zhang, Guojie Luo:
An Endeavor to Industrialize Hardware Fuzzing: Automating NoC Verification in UVM. 1-2 - Yinuo Bai, Xiaoyu Yang, Yicheng Lu, Dan Niu, Cheng Zhuo, Zhou Jin, Weifeng Liu:
Efficient Spectral-Aware Power Supply Noise Analysis for Low-Power Design Verification. 1-6 - Hongduo Liu, Peiyu Liao, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu:
Parallel Gröbner Basis Rewriting and Memory Optimization for Efficient Multiplier Verification. 1-6 - Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich:
Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. 1-2 - Enxin Yi, Yiru Duan, Yinuo Bai, Kang Zhao, Zhou Jin, Weifeng Liu:
Cuper: Customized Dataflow and Perceptual Decoding for Sparse Matrix-Vector Multiplication on HBM-Equipped FPGAs. 1-6 - Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint. 1-6 - Ya Wang, Hanwei Fan, Sicheng Li, Tingyuan Liang, Wei Zhang:
A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration. 1-6 - Jiajie Xu, Leilei Jin, Wenjie Fu, Longxing Shi:
A Deep-Learning-Based Statistical Timing Prediction Method for Sub-16nm Technologies. 1-6 - Donger Luo, Qi Sun, Qi Xu, Tinghuan Chen, Hao Geng:
Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metrics. 1-6 - Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, Yao-Wen Chang:
Electrostatics-Based Analytical Global Placement for Timing Optimization. 1-6 - Mirco De Marchi, Cristian Turetta, Graziano Pravadelli, Nicola Bombieri:
Real-Time Multi-Person Identification and Tracking via HPE and IMU Data Fusion. 1-6 - Yuya Isaka, Nau Sakaguchi, Michiko Inoue, Michihiro Shintani:
EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing. 1-6 - Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo:
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs. 1-6 - Hai Helen Li:
AI Models for Edge Computing: Hardware-aware Optimizations for Efficiency. 1 - Yun-Chih Chen, Yuan-Hao Chang, Tei-Wei Kuo:
Search-in-Memory (SiM): Conducting Data-Bound Computations on Flash Chip for Enhanced Efficiency. 1-2 - Rahul Vishwakarma, Amin Rezaei:
Uncertainty-Aware Hardware Trojan Detection Using Multimodal Deep Learning. 1-6 - Febin Sunny, Amin Shafiee, Benoît Charbonnier, Mahdi Nikdast, Sudeep Pasricha:
COMET: A Cross-Layer Optimized Optical Phase-Change Main Memory Architecture. 1-6 - Yun Chen, Arash Pashrashid, Yongzheng Wu, Trevor E. Carlson:
Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone. 1-6 - Nurun Nahar Mondol, Arash Vafaei, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation. 1-6 - Mehrdad Morsali, Sepehr Tabrizchi, Deniz Najafi, Mohsen Imani, Mahdi Nikdast, Arman Roohi, Shaahin Angizi:
OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing. 1-6 - Alexandra Küster, Rainer Dorsch, Christian Haubelt:
Adaptive ODE Solvers for Timed Data Flow Models in SystemC-AMS. 1-6 - Jonas Crols, Guilherme Paim, Shirui Zhao, Marian Verhelst:
TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware. 1-6 - Cristiana Bolchini, Alberto Bosio:
Resilience of Deep Learning Applications: Where We are and Where We Want to Go. 1 - Seyedarmin Azizi, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram:
Automated Optimization of Deep Neural Networks: Dynamic Bit-Width and Layer-Width Selection via Cluster-Based Parzen Estimation. 1-6 - Jhon Ordoñez, Chengmo Yang:
Derailed: Arbitrarily Controlling DNN Outputs with Targeted Fault Injection Attacks. 1-6 - Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang:
A Hybrid Approach to Reverse Engineering on Combinational Circuits. 1-2 - Yuxuan Yin, Xiaoxiao Wang, Rebecca Chen, Chen He, Peng Li:
Reliable Interval Prediction of Minimum Operating Voltage Based on On-Chip Monitors via Conformalized Quantile Regression. 1-6 - Zhou Jin, Tian Feng, Xiao Wu, Dan Niu, Zhenya Zhou, Cheng Zhuo:
MSH: A Multi-Stage HiZ-Aware Homotopy Framework for Nonlinear DC Analysis. 1-6 - Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. 1-6 - Seungju Lee, Kyumin Cho, Eunji Kwon, Sejin Park, Seojeong Kim, Seokhyeong Kang:
ViT- ToGo: Vision Transformer Accelerator with Grouped Token Pruning. 1-6 - Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini:
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation. 1-6 - Matthew Edwin Weingarten, Nora Hossle, Timothy Roscoe:
High Throughput Hardware Accelerated CoreSight Trace Decoding. 1-6 - Mengnan Jiang, Jingcun Wang, Amro Eldebiky, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Grace Li Zhang:
Class-Aware Pruning for Efficient Neural Networks. 1-6 - Kaichang Chen, Georges G. E. Gielen:
Self-Learning and Transfer Across Topologies of Constraints for Analog / Mixed-Signal Circuit Layout Synthesis. 1-6 - Nastaran Darabi, Priyesh Shukla, Dinithi Jayasuriya, Divake Kumar, Alex C. Stutts, Amit Ranjan Trivedi:
Navigating the Unknown: Uncertainty-Aware Compute-in-Memory Autonomy of Edge Robotics. 1-6 - Ruide Cao, Jiao Ye, Jin Zhang, Qian You, Chao Tang, Yan Liu, Yi Wang:
An Adaptive UAV Scheduling Process to Address Dynamic Mobile Network Demand Efficiently. 1-6 - Giulia Elena Aliffi, Joao Baixinho, Dalibor Barri, Francesco Daghero, Nicola Di Carolo, Gabriele Faraone, Michelangelo Grosso, Daniele Jahier Pagliari, Jiri Jakovenko, Vladimír Janícek, Dario Licastro, Vazgen Melikyan, Matteo Risso, Vittorio Romano, Eugenio Serianni, Martin Stastný, Patrik Vacula, Giorgia Vitanza, Chen Xie:
AMBEATion: Analog Mixed-Signal Back-End Design Automation with Machine Learning and Artificial Intelligence Techniques. 1-6 - Hongfei Wang, Chenliang Luo, Deqing Zou, Hai Jin, Wenjie Cai:
Gradient Boosting-Accelerated Evolution for Multiple-Fault Diagnosis. 1-6 - Vikash Kumar, Behnaz Ranjbar, Akash Kumar:
Motivating the Use of Machine-Learning for Improving Timing Behaviour of Embedded Mixed-Criticality Systems. 1-2 - Daniel Schönberger, Stefan Hillmich, Matthias Brandl, Robert Wille:
Towards Cycle-based Shuttling for Trapped-Ion Quantum Computers (Extended Abstract). 1-2 - Khaled Alamin, Daniele Jahier Pagliari, Yukai Chen, Enrico Macii, Sara Vinco, Massimo Poncino:
Model-Driven Feature Engineering for Data-Driven Battery SOH Model. 1-6 - Maria Emmerich, Philipp Ebner, Robert Wille:
Design Automation for Organs-on-Chip. 1-6 - Siyu Zhang, Wendong Mao, Huihong Shi, Zhongfeng Wang:
A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid Network. 1-6 - Manaar Alam, Yue Wang, Michail Maniatakos:
Detecting Backdoor Attacks in Black-Box Neural Networks through Hardware Performance Counters. 1-6 - Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy:
Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption. 1-6 - Paul R. Genssler, Mahta Mayahinia, Simon Thomann, Mehdi B. Tahoori, Hussam Amrouch:
DropHD: Technology/Algorithm Co-Design for Reliable Energy-Efficient NVM-Based Hyper-Dimensional Computing Under Voltage Scaling. 1-6 - Justin Davis, Mehmet E. Belviranli:
Context-aware Multi-Model Object Detection for Diversely Heterogeneous Compute Systems. 1-6 - Anna Lena Duque Antón, Johannes Müller, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators. 1-6 - Lei Xun, Mingyu Hu, Hengrui Zhao, Amit Kumar Singh, Jonathon S. Hare, Geoff V. Merrett:
Fluid Dynamic DNNs for Reliable and Adaptive Distributed Inference on Edge Devices. 1-2 - Ilkin Aliyev, Tosiron Adegbija:
Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks. 1-2 - Sasan Razmkhah, Robert S. Aviles, Mingye Li, Sandeep Gupta, Peter A. Beerel, Massoud Pedram:
Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital Logic. 1-6 - Shivam Aggarwal, Kuluhan Binici, Tulika Mitra:
CRISP: Hybrid Structured Sparsity for Class-Aware Model Pruning. 1-6 - Minah Lee, Sudarshan Sharma, Wei Chun Wang, Hemant Kumawat, Nael Mizanur Rahman, Saibal Mukhopadhyay:
Cognitive Sensing for Energy-Efficient Edge Intelligence. 1-6 - Jianfeng Song, Rongjian Liang, Yu Gong, Bo Yuan, Jiang Hu:
DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture. 1-6 - Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Mueller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, Wolfgang Ecker:
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. 1-5 - Aditya S. Gangwar, Prathamesh Nitin Tanksale, Shirshendu Das, Sudeepta Mishra:
$\mathcal{F}lush+early\mathcal{R}\text{ELOAD}$: Covert Channels Attack on Shared LLC Using MSHR Merging. 1-6 - Mahta Mayahinia, Simon Thomann, Paul R. Genssler, Christopher Münch, Hussam Amrouch, Mehdi B. Tahoori:
Algorithm to Technology Co-Optimization for CiM-Based Hyperdimensional Computing. 1-6 - Justin McGowen, Ismet Dagli, Neil T. Dantam, Mehmet E. Belviranli:
Constraint-Aware Resource Management for Cyber-Physical Systems. 1-2 - Bahador Rashidi, Shan Lu, Kiarash Aghakasiri, Chao Gao, Fred Xuefei Han, Zhisheng Wang, Laiyuan Gong, Fengyu Sun:
CASCO: Cascaded Co-Optimization for Holistic Neural Network Acceleration. 1-6 - Spyridon Spyridonos, Yiorgos Tsiatouhas:
Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories. 1-6 - Weihong Xu, Jaeyoung Kang, Tajana Rosing:
AttBind: Memory-Efficient Acceleration for Long-Range Attention Using Vector-Derived Symbolic Binding. 1-6
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