default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID18th DDECS 2015: Belgrade, Serbia
- Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus:
18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-6779-7
Session 1A: ATPG & Test Compression
- Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier:
TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. 3-8 - Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs. 9-14
Session 1B: Design Architectures & Synthesis
- Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus, Enrico Altmann, Horst Seelig:
Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP. 17-22 - I-Che Chen, John P. Hayes:
Low-Area and High-Speed Approximate Matrix-Vector Multiplier. 23-28
Session 2A: Digital Design
- Tetsuya Matsumura, Aoi Kurokawa, Kousuke Imamura, Yoshio Matsuda:
A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm. 31-36 - Filip Kodýtek
, Róbert Lórencz:
A Design of Ring Oscillator Based PUF on FPGA. 37-42 - Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot:
Design-for-Diagnosis Architecture for Power Switches. 43-48
Session 2B: Analog Circuits
- Sneana Stefanovski, Milka M. Potrebic, Dejan Toic, Zoran Stamenkovic:
A Novel Compact Dual-Band Bandpass Waveguide Filter. 51-56 - Daniel Arbet, Gabriel Nagy, Martin Kovác, Viera Stopjaková:
Fully Differential Difference Amplifier for Low-Noise Applications. 57-62 - Andrzej Grodzicki, Witold A. Pleskacz:
A Low Ripple Current Mode Voltage Doubler. 63-68
Poster Session I
- Syed Saif Abrar, Maksim Jenihhin, Jaan Raik:
SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores. 71-74 - Thomas Hollstein, Siavoosh Payandeh Azad, Thilo Kogge, Haoyuan Ying, Klaus Hofmann:
NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip. 75-78 - Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang:
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. 79-82 - Lukás Nagy, Viera Stopjaková, Alexander Satka:
Design of In AlN/GaN Heterostructure-Based Logic Cells. 83-86 - Hong-Yi Huang, Gene Fe P. Palencia, Da-Kai Chen, Wei-Hsuan Huang:
Triangular Modulation Using Switched-Capacitor Scheme for Spread-Spectrum Clocking. 87-90 - Michaela Beleova, Zdenek Kotásek, Marcela Simková, Toma Hruka:
Application of Evolutionary Algorithms for Regression Suites Optimization. 91-94 - Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das:
Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits. 95-98 - Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus:
Combining Correction of Delay Faults and Transient Faults. 99-102 - Mikhail Glukhikh, Mikhail J. Moiseev:
Fast Simulation of SystemC Synthesizable Subset. 103-106 - Marco Giammarini, Daniela Isidori, Enrico Concettoni, Cristina Cristalli, Matteo Fioravanti, Marco Pieralisi:
Design of Wireless Sensor Network for Real-Time Structural Health Monitoring. 107-110 - Nikolay N. Prokopenko, Nikolay V. Butyrlagin, Sergei G. Krutchinsky, Evgeniy A. Zhebrun, Alexey E. Titov:
The Advanced Circuitry of the Precision Super Capacitances Based on the Classical and Differential Difference Operational Amplifiers. 111-114 - Rados Dabic, Sasa Jednak, Ilija Adzic, Dusko Stanic, Aleksandar Mijatovic, Stanislav Vuckovic:
Direct Test Methodology for HDL Verification. 115-118 - Spyridon Nikolaidis:
Modeling CMOS Gates Using Equivalent Inverters. 119-122 - Maciej Moskala, Patryk Kloczko, Marek Cieplucha, Witold A. Pleskacz:
UVM-based Verification of Bluetooth Low Energy Controller. 123-124 - Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou:
PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. 125-128
Session 3A: Modeling and Simulation
- Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. 131-136 - Dusan N. Grujic, Mihajlo Bozovic, Milan Savic:
BSIM4 to PSP Model Conversion for Passive Mixer IM3 Simulation. 137-142
Session 3B: Student Session
- Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek:
FPGA Prototyping and Accelerated Verification of ASIPs. 145-148 - Ioana Mot, Oana Boncalo, Alexandru Amaricai:
Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques. 149-152 - Miroslav Siebert, Elena Gramatová:
Parameterized Critical Path Selection for Delay Fault Testing. 153-156 - Martin Krcma, Jan Kastil, Zdenek Kotásek:
Mapping Trained Neural Networks to FPNNs. 157-160 - Muhammed Ceylan Morgül, Mustafa Altun:
Synthesis and Optimization of Switching Nanoarrays. 161-164 - Vasileios Gerakis, Fontounasios Christos, Alkis A. Hatzopoulos:
Modeling the Coupling through Substrate for Frequencies up to 100GHz. 165-168
Session 4A: Formal Verification
- Nils Przigoda, Robert Wille, Rolf Drechsler:
Contradiction Analysis for Inconsistent Formal Models. 171-176 - Niels Thole, Heinz Riener, Görschwin Fey:
Equivalence Checking on System Level Using a Priori Knowledge. 177-182 - Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler:
Requirement Phrasing Assistance Using Automatic Quality Assessment. 183-188
Session 4B: Design Enhancement
- Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic:
A Design Preconditioning Flow for Low-Noise Circuits. 191-196 - Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger:
Containment of Metastable Voltages in FPGAs. 197-202 - Vladimir Petrovic, Milos Krstic:
Design Flow for Radhard TMR Flip-Flops. 203-208
Session 5A: Wear-Out & Intermittent Faults
- Hans G. Kerkhoff, Hassan Ebrahimi:
Intermittent Resistive Faults in Digital CMOS Circuits. 211-216 - Milan Babic, Milos Krstic:
A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates. 217-222 - Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls:
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. 223-228
Session 5B: Measurement & Analysis
- Goran Panic, Zoran Stamenkovic:
Activity Profiling and Power Estimation for Embedded Wireless Sensor Node Design. 231-236 - Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
Embedded Test Instrument for On-Chip Phase Noise Evaluation of Analog/IF Signals. 237-242 - Shuichi Sato, Satoshi Ohtake:
A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model. 243-248
Poster Session II
- Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar:
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. 251-254 - Marko S. Andjelkovic, Vladimir Petrovic, Zoran Stamenkovic, Goran S. Ristic, Goran S. Jovanovic:
Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch. 255-258 - Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Power-Management Specification in SystemC. 259-262 - Lukasz Lopacinski, Jörg Nolte, Steffen Büchner, Marcin Brzozowski, Rolf Kraemer:
Design and Implementation of an Adaptive Algorithm for Hybrid Automatic Repeat Request. 263-266 - Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko:
Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit. 267-270 - Krzysztof Marcinek, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz:
Implementation of the ADELITE Microcontroller for Biomedical Applications. 271-274 - Francesco Cannone, Gianfranco Avitabile, Giuseppe Coviello, Giovanni Piccinni:
High Precision Digital Based 3.8GHz Phase Shifter. 275-278 - Stefan Kristofík, Marcel Baláz, Mária Fischerová:
Generic Self Repair Architecture with On-Line Fault Diagnosis. 279-282 - Nikolay N. Prokopenko, Nikolay V. Butyrlagin, Sergei G. Krutchinsky, Evgeniy A. Zhebrun, Alexey E. Titov:
Microwave Selective Amplifiers with High Asymptotic Attenuation in the Range of Subresonance Frequencies. 283-286 - Nebojsa Pjevalica, Milos Nikolic, Ivan Kastelan:
Analog Circuitry for BLDC Motor Magnetic Saturation Diagnostic. 287-290 - Peter Malík:
High Throughput Floating-Point Dividers Implemented in FPGA. 291-294 - Thilo Vörtler, Benny Höckner, Petra Hofstedt, Thomas Klotz:
Formal Verification of Software for the Contiki Operating System Considering Interrupts. 295-298 - David L. Larkai, Ruiheng Wu:
Wireless Heart Rate Monitor in Personal Emergency Response System. 299-300 - Mladen Cicic, Jesús Gutiérrez Terán, Zoran Stamenkovic:
Hardware Implementation of a RSS Localization Algorithm for Wireless Capsule Endoscopy. 301-304
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-09-19 23:51 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
