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ORCID22nd DDECS 2019: Cluj-Napoca, Romania
- 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2019, Cluj-Napoca, Romania, April 24-26, 2019. IEEE 2019, ISBN 978-1-7281-0073-9
- Stanislav Jerabek
, Jan Schmidt:
Analyzing and Optimizing the Dummy Rounds Scheme. 1-4 - Michal Skuta, Dominik Macko:
Automated Integration of Dynamic Power Management into FPGA-Based Design. 1-4 - Karel Szurman, Zdenek Kotásek:
Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430. 1-4 - Sebastian Pointner, Pablo González de Aledo, Robert Wille:
Generic Error Localization for the Electronic System Level. 1-4 - Hwann-Kaeo Chiou, Wei-Min Sung:
A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider. 1-4 - Muhammad Tanweer, Kari A. I. Halonen:
Development of wearable hardware platform to measure the ECG and EMG with IMU to detect motion artifacts. 1-4 - Martin Strava:
Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures. 1-4 - Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. 1-4 - Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold A. Pleskacz:
Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter. 1-4 - F. Almeida, Paolo Bernardi, D. Calabrese, Marco Restifo, Matteo Sonza Reorda, Davide Appello, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli, Gulio Zoppi:
Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test. 1-6 - Ioana Lal, Marius Nicoara, Alexandru Codrean, Lucian Busoniu:
Hardware and control design of a ball balancing robot. 1-6 - Andrea Floridia, Gianmarco Mongano, Davide Piumatti, Ernesto Sánchez:
Hybrid on-line self-test architecture for computational units on embedded processor cores. 1-6 - Vlad Muresan, Mihail Abrudean:
Fault Tolerant Control System of the Rotary Hearth Furnace Servicing Machines. 1-6 - Amin Malekpour, Roshan G. Ragel, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran:
Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing. 1-6 - Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Viera Stopjaková:
Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology. 1-6 - Konstantin O. Petrosyants, Maxim V. Kozhukhov, Dmitry Popov:
Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI's Components using RAD-THERM TCAD Subsystem. 1-4 - Tomas Fukac, Jan Korenek:
Hash-based Pattern Matching for High Speed Networks. 1-5 - Attila Fejér, Zoltán Nagy, Jenny Benois-Pineau, Péter Szolgay, Aymar de Rugy, Jean-Philippe Domenger:
FPGA-based SIFT implementation for wearable computing. 1-4 - Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Encryption-Based Secure JTAG. 1-6 - Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng:
A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System. 1-4 - Lukasz Lopacinski, Mohamed Hussein Eissa, Goran Panic, Alireza Hasani, Rolf Kraemer:
Modular Data Link Layer Processing for THz communication. 1-5 - Roman Vrana, Jan Korenek, David Novak:
Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. 1-6 - Lukás Kohútka, Lukás Nagy, Viera Stopjaková:
Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems. 1-6 - Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang:
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. 1-2 - Ondrej Novák:
Nonlinear Compression Codes Used In IC Testing. 1-4 - Sergei Odintsov, Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Artur Jutman:
A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network. 1-6 - Jan Belohoubek, Petr Fiser, Jan Schmidt:
Using Voters May Lead to Secret Leakage. 1-4 - Ching-Hwa Cheng, Tang-Chieh Liu:
Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems. 1-4 - Tsung-Han Tsai, Yuan-Chen Ho, Ming-Hwa Sheu:
Implementation of FPGA-based Accelerator for Deep Neural Networks. 1-4 - Miroslav Potocný, Juraj Brenkus, Viera Stopjaková:
High side power MOSFET switch driver for a low-power AC/DC converter. 1-6 - Martin Kovác, Daniel Arbet, Viera Stopjaková, Michal Sovcik, Lukás Nagy:
Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology. 1-4 - Andreas Krinke, Tilman Horst, Georg Gläser, Martin Grabmann, Tobias Markus, Benjamin Prautsch, Uwe Hatnik, Jens Lienig:
From Constraints to Tape-Out: Towards a Continuous AMS Design Flow. 1-10 - Jan Malburg, Karl Janson, Jaan Raik, Frank Dannemann:
Fault-Aware Performance Assessment Approach for Embedded Networks. 1-4 - Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen:
Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. 1-4 - Stefano Di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
On the in-field test of the GPGPU scheduler memory. 1-6
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