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ORCIDETS 2006: Southhampton, UK
- 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006. IEEE Computer Society 2006, ISBN 0-7695-2566-0
Plenary Presentations
- Robin Saxby:
Innovation and Wealth Creation from Technology. 3 - Steve B. Furber
:
Living with Failure: Lessons from Nature? 4-8
Delay Fault Testing
- Gefu Xu, Adit D. Singh:
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. 9-14 - Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod:
Dynamic Voltage Scaling Aware Delay Fault Testing. 15-20 - Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi:
Enhancing Delay Fault Coverage through Low Power Segmented Scan. 21-28
Single-Event Upsets
- Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto:
Single-Event Upset Analysis and Protection in High Speed Circuits. 29-34 - Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee:
Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study. 35-42
Memory Testing - 1
- Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March Tests for Dynamic Faults in Random Access Memories. 43-48 - Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
A 22n March Test for Realistic Static Linked Faults in SRAMs. 49-54 - Yu-Jen Huang, Jin-Fu Li:
Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. 55-62
Test of Reconfiguration Systems
- Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. 63-68 - Kentaroh Katoh, Hideo Ito:
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. 69-74 - Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena:
Fault Injection-based Reliability Evaluation of SoPCs. 75-82
Memory Testing - 2
- Qiang Xu, Baosheng Wang, F. Y. Young:
Retention-Aware Test Scheduling for BISTed Embedded SRAMs. 83-88 - Slimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa:
A Transparent based Programmable Memory BIST. 89-96
Test and Measurement
- Bernd Laquai, Martin Hua, Guido Schulze, Michael Braun:
A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare. 97-102 - Matthew Collins, Bashir M. Al-Hashimi:
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution. 103-110
BIST and Test Data Compression for Logic
- Ramashis Das, Igor L. Markov, John P. Hayes:
On-Chip Test Generation Using Linear Subspaces. 111-116 - Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Convolutional Compactors with Variable Polynomials. 117-122 - Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers:
Deterministic Logic BIST for Transition Fault Testing. 123-130
Test of Sigma-Delta Modulators
- Gildas Léger, Adoración Rueda:
Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators. 131-136 - Erik Schüler, Daniel Scain Farenzena, Luigi Carro:
Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits. 137-144
Current-Based and Power Switch Testing
- Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez:
Testing and Diagnosis of Power Switches in SOCs. 145-150 - Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret:
A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications. 151-158
Test of AD and DA Circuits
- Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell:
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. 159-164 - Shalabh Goyal, Abhijit Chatterjee, Mike Atia:
Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test. 165-172
Automatic Test Pattern Generation
- Irith Pomeranz, Sudhakar M. Reddy:
Fault Collapsing for Transition Faults Using Extended Transition Faults. 173-178 - Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
FATE: a Functional ATPG to Traverse Unstabilized EFSMs. 179-184 - Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. 185-192
Advanced Analog Testing
- Vincent Fresnaud, Lilian Bossuet, Dominique Dallet, Serge Bernard, Jean-Marie Janik, B. Agnus, Philippe Cauvet, Ph. Gandy:
A Low Cost Alternative Method for Harmonics Estimation in a BIST Context. 193-198 - Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham:
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters. 199-204 - Donghoon Han, Shalabh Goyal, Soumendu Bhattacharya, Abhijit Chatterjee:
Low Cost Parametric Failure Diagnosis of RF Transceivers. 205-212
Test of Asynchronous and NOC Circuitry
- Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes:
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. 213-218 - Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach:
A DFT Architecture for Asynchronous Networks-on-Chip. 219-224 - Delong Shang, Alexandre Yakovlev, Frank P. Burns, Fei Xia, Alexandre V. Bystrov:
Low-Cost Online Testing of Asynchronous Handshakes. 225-232
Diagnosis
- Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
Test-per-Clock Detection, Localization and Identification of Interconnect Faults. 233-238 - Frank Poehl, Jan Rzeha, Matthias Beck, Michael Gössel, Ralf Arnold, Peter Ossimitz:
On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture. 239-246
Embedded Tutorials
- Tino Heijmen, André Nieuwland:
Soft-Error Rate Testing of Deep-Submicron Integrated Circuits. 247-252 - Bill Eklow, Ben Bennetts:
New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG). 253-254
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