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ORCIDNORCHIP 2014: Tampere, Finland
- 2014 NORCHIP, Tampere, Finland, October 27-28, 2014. IEEE 2014
- Dennis Oland Larsen, Pere Llimos Muntal
, Ivan H. H. Jørgensen, Erik Bruun:
High-voltage pulse-triggered SR latch level-shifter design considerations. 1-6 - Timo Rahkonen, Christian Schuss, Mikko Hietanen, T. Kotikumpu, J. Mustajarvi, A. Myllymaki:
Electronics for characterizing and using photovoltaics. 1-4 - Niels Marker-Villumsen, Erik Bruun:
Optimization of modulator and circuits for low power continuous-time Delta-Sigma ADC. 1-6 - Muhammad Touqir Pasha, Mark Vesterbacka:
A modified switching scheme for multiplexer based thermometer-to-binary encoders. 1-4 - Roman Marsálek, Martin Pospísil:
Evaluation of digital predistortion using the USRP N200 software defined radio transceiver. 1-4 - Ali Vahdati, Mikko Varonen, Mikko Kärkkäinen, Dristy Parveg, Kari Halonen:
A 97-106-GHz differential I-Q phase shifter in 28-nm CMOS. 1-4 - Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, Radi Husin Bin Ramlee, Mark Zwolinski:
Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs. 1-4 - Nan Li, Elena Dubrova, Gunnar Carlsson:
Evaluation of alternative LBIST flows: A case study. 1-5 - Pere Llimos Muntal, Dennis Oland Larsen, Ivan H. H. Jørgensen, Erik Bruun:
Integrated reconfigurable high-voltage transmitting circuit for CMUTs. 1-4 - Tuan Nguyen Gia, Nanda Kumar Thanigaivelan, Amir-Mohammad Rahmani, Tomi Westerlund, Pasi Liljeberg, Hannu Tenhunen:
Customizing 6LoWPAN networks towards Internet-of-Things based ubiquitous healthcare systems. 1-6 - Dmitry Lukyanov, Sergey Yu. Shevchenko, Alexander S. Kukaev, E. Filippova, D. Safronov:
Micromechanical accelerometers based on surface acoustic waves. 1-4 - Abdelrahman H. Radwan, Ahmad M. Marzouk, Mohamed A. Abd El-Ghany, Klaus Hofmann:
An efficient maximum power point tracking algorithm for solar PV panels. 1-4 - Ji Wang, Manuel Bejarano Carmona, Helgi Hall, Dejan Radjen, Ping Lu:
A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio. 1-4 - Hitoshi Hayashi:
Tandem Lange 3-dB 90° hybrid implemented on FR4 substrate. 1-3 - Mika Kutila, Marko Ylitolva, Jonas Eriksson:
Design solutions for a low-power SoC platform using near-threshold voltages. 1-4 - Lebo Wang, Youde Hu, Li-Rong Zheng, Jue Shen, Zhuo Zou:
Design of wideband mixer and VGA for Software Defined Radio in RFID application. 1-4 - Antti Mäntyniemi, Juha Kostamovaara:
Time-to-digital converter (TDC) based on startable ring oscillators and successive approximation. 1-4 - Peter Nilsson, Ateeq Ur Rahman Shaik, Rakesh Gangarajaiah, Erik Hertz:
Hardware implementation of the exponential function using Taylor series. 1-4 - Jakob Kenn Toft, Alberto Nannarelli:
Energy efficient FPGA based hardware accelerators for financial applications. 1-6 - Tobias Tired, Henrik Sjöland, Per Sandrup, Johan Wernehag, Imad ud Din, Markus Törmänen:
A 28 GHz SiGe QVCO and divider for an 81-86 GHz E-band beam steering transmitter PLL. 1-4 - Dmitry Lukyanov, Sergey Yu. Shevchenko, Alexander S. Kukaev, A. Ivanov, R. Telichkin:
Micro rate gyroscopes based on surface acoustic waves. 1-4 - Dejan Radjen, Martin Anderson, Lars Sundström, Pietro Andreani:
A low-power 2nd-order CT ΔΣ modulator with an asynchronous SAR quantizer. 1-4 - Jue Shen, Fredrik Jonsson, Jian Chen, Hannu Tenhunen, Li-Rong Zheng:
Phase noise improvement and noise modeling of type-I ADPLL with non-linear quantization effects. 1-4 - Federica Resta, Stefano D'Amico, Marcello De Matteis, Andrea Baschirotto:
An improved source-follower based Sallen-Key continuous-time biquadratic cell with auxiliary path. 1-4 - Christoph Thomas Muller, Evangelia Kasapaki, Rasmus Bo Sørensen, Jens Sparsø:
Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools. 1-6 - Shailesh Singh Chouhan, Kari Halonen:
Voltage multiplier circuit for UHF RF to DC conversion for RFID applications. 1-4 - Magne Voernes, Trond Ytterdal, Snorre Aunet:
Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout. 1-6 - Nguyen Duc Bui Phong, Masoud Daneshtalab, Sergei Dytckov, Juha Plosila, Hannu Tenhunen:
Silicon synapse designs for VLSI neuromorphic platform. 1-6 - Martin Nielsen-Lönn, J. Jacob Wikner, Atila Alvandpour:
Design considerations for interface circuits to low-voltage piezoelectric energy harvesters. 1-4 - Siavoosh Payandeh Azad, Nasim Farahini, Ahmed Hemani:
Customization methodology of a Coarse Grained Reconfigurable architecture. 1-4 - Oana Boncalo, Alexandru Amaricai, Christian Spagnol, Emanuel M. Popovici:
Cost effective FPGA probabilistic fault emulation. 1-4 - Stefan Hänzsche, Sebastian Höppner, René Schüffny:
A 10 bit 16 MS/s redundant SAR ADC with flexible window function for a digitally controlled DC-DC converter in 28 nm CMOS. 1-4 - Janne Aikio, Timo Rahkonen:
Polynomial modelling: Accuracy vs. shape. 1-4 - Tapani Nevalainen, Tero Koivisto, Mikko Pänkäälä:
Subthreshold nano-watt front-end amplifier for wireless ECG applications. 1-4 - Jesper Johansson, Lars Svensson:
A novel speculative pseudo-parallel ΔΣ modulator. 1-4 - Mathias Herlev, Christian Keis Poulsen, Jens Sparsø:
Open core protocol (OCP) clock domain crossing interfaces. 1-6 - Soo-Woo Kim, Se-Hyuk An, Nam-Soo Kim, Hye-Im Jeong, Ho-Yong Choi:
Circuit design for broad band EMI reduction in LCD driver IC. 1-4 - Kin Keung Lee, Tor Sverre Lande:
A 5.3 pJ/pulse impulse-radio ultra-wideband pulse-generator for band group # 6. 1-4 - Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici:
A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces. 1-4 - Vacius Jusas, Tomas Neverdauskas:
Stimuli generator for testing processes in VHDL. 1-4 - Janko Katic, Saul Rodriguez, Ana Rusu:
Analysis of dead time losses in energy harvesting boost converters for implantable biosensors. 1-4 - Olli Kursu, Timo Rahkonen:
Integrated circuit for neural recording and stimulation. 1-4 - Ilkka Nissinen, Jan Nissinen, Jouni Holma, Juha Kostamovaara:
Cross talk measurements of a time-gated 4×128 SPAD array for pulsed Raman spectroscopy. 1-4 - Prakash Harikumar, J. Jacob Wikner:
Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump. 1-4 - Yue Qian, Junhui Wang:
Analyzing Worst-case Delay-Buffer-Equation for wormhole networks on chip. 1-6 - Ming Liu, Elena Dubrova:
An new approach to reliable FSRs lDesign. 1-4 - Jonathan Edvard Bjerkedok, Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet:
Modular layout-friendly cell library design applied for subthreshold CMOS. 1-6 - Muh-Dey Wei, Sheng-Fuh Chang, Renato Negra:
Design of low phase noise K-band Voltage-Controlled Oscillator using 180 nm CMOS and integrated passive device technologies. 1-4 - Elena Dubrova, Mats Näslund, Göran Selander, Vlasios Tsiatsis:
Energy-efficient message authentication for IEEE 802.15.4-based wireless sensor networks. 1-4 - Yangxurui Liu, Liang Liu, Viktor Öwall, Shuming Chen:
Implementation of a dynamic wordlength SIMD multiplier. 1-4 - Hussein Ezzeddine, Johnny Öberg, Francesco Robino:
Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite. 1-6
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