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ORCID33rd SoCC 2020: Las Vegas, NV, USA
- 33rd IEEE International System-on-Chip Conference, SoCC 2020, Las Vegas, NV, USA, September 8-11, 2020. IEEE 2020, ISBN 978-1-7281-8746-4
- Sai Praveen Kadiyala, Mohit Garg, Manaar Alam
, Hau T. Ngo, Debdeep Mukhopadhyay, Thambipillai Srikanthan:
HARDY: Hardware based Analysis for malwaRe Detection in embedded sYstems. 1-6 - Yuchen Mei, Li Du, Xuewen He, Yuan Du, Xiaoliang Chen, Zhongfeng Wang:
A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security. 7-12 - Fahad Siddiqui, Sakir Sezer:
Evolution of Embedded Platform Security Technologies: Past, Present & Future Challenges. 13-18 - Ziming Wang, Aijiao Cui, Gang Qu:
A Low-Cost Fault Injection Attack Resilient FSM Design. 19-24 - Jinyu Zhan, Ying Li, Wei Jiang, Jianping Zhu:
FPGA Based Co-design of Storage-side Query Filter for Big Data Systems. 25-30 - Rui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Liang Shi, Shouzhen Gu:
Architectural Exploration on Racetrack Memories. 31-36 - Geng Yuan, Xiaolong Ma, Sheng Lin, Zhengang Li, Jieren Deng, Caiwen Ding:
A DNN Compression Framework for SOT-MRAM-based Processing-In-Memory Engine. 37-42 - Basel Halak, Jorge Duarte-Sanchez:
Cube Attack on a Trojan-Compromised Hardware Implementation of Ascon. 43-47 - Rohini J. Gillela, Amlan Ganguly, Dorin Patru, Mark A. Indovina:
The IANET Hardware Accelerator for Audio and Visual Data Classification. 48-53 - Arnab Neelim Mazumder, Hasib-Al Rashid, Tinoosh Mohsenin:
An Energy-Efficient Low Power LSTM Processor for Human Activity Monitoring. 54-59 - Sai Govinda Rao Nimmalapudi, Andrew Marshall, Harvey Stiegler, Keith Jarreau:
Self-Correcting Op-Amp Input Offset Using Analog Floating Gates. 60-65 - Jingyan Fu, Zhiheng Liao, Jinhui Wang:
Cycle-to-cycle Variation Enabled Energy Efficient Privacy Preserving Technology in ANN. 66-71 - Binayak Tiwari, Mei Yang, Xiaohang Wang, Yingtao Jiang, Venkatesan Muthukumar:
Improving the Performance of a NoC-based CNN Accelerator with Gather Support. 72-77 - Kris Min, Brenda Ly, Joshua Garner, Shahnam Mirzaei:
A Novel Method for Hardware Acceleration of Convex Hull Algorithm on Reconfigurable Hardware. 78-83 - Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang:
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. 84-89 - Shaoxia Fang, Shulin Zeng, Yu Wang:
Optimizing CNN Accelerator With Improved Roofline Model. 90-95 - Taha Soliman, Ricardo Olivo, Tobias Kirchner, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn:
A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks. 96-101 - Haoran Ren, Arnab Neelim Mazumder, Hasib-Al Rashid, Vandana Chandrareddy, Aidin Shiri, Nitheesh Kumar Manjunath, Tinoosh Mohsenin:
End-to-end Scalable and Low Power Multi-modal CNN for Respiratory-related Symptoms Detection. 102-107 - Chuangtao Chen, Qingrong Huang, Chao Li, Li Zhang, Cheng Zhuo, Xunzhao Yin:
Analog Content Addressable Memory using Ferroelectric: A Case Study of Search-in-Memory. 108-112 - Erxiang Ren, Li Luo, Zheyu Liu, Fei Qiao, Qi Wei:
C2IM: A Compact Computing-In-Memory Unit of 10 Transistors with Standard 6T SRAM. 113-116 - Li Yang, Zhezhi He, Shaahin Angizi, Deliang Fan:
Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency. 117-122 - Mohsen Imani, Saransh Gupta, Yeseong Kim, Tajana Rosing:
Deep Learning Acceleration using Digital-Based Processing In-Memory. 123-128 - Vikas Rana, Shivam Kalla:
Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping Efficiency. 129-134 - Mohammad Taherifard, Hakem Beitollahi, Fateme Jamali, Amin Norollah, Ahmad Patooghy:
Mist-Scan: A Secure Scan Chain Architecture to Resist Scan-Based Attacks in Cryptographic Chips. 135-140 - Tung-Liang Lin, Sao-Jie Chen:
DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature Variations. 141-146 - Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang:
A High-Speed Architecture for the Reduction in VDF Based on a Class Group. 147-152 - Yuchen Zhao, Zhuo Zou, Lirong Zheng:
An Inverter-based On-chip Voltage Reference Generator for Low Power Application. 153-157 - Jianhua Zhang, Ming Zou, Lai Wei, Meng Ma, Bingli Jiao:
Downlink-Centric User Scheduling for Full-Duplex MU-MIMO Systems. 158-162 - Aasish Boora, Bharatha Kumar Thangarasu, Kiat Seng Yeo:
An Ultra-Low Power 900 MHz Intermediate Frequency Low Noise Amplifier For Low-Power RF Receivers. 163-167 - Xiao Wu, Yufei Ma, Zhongfeng Wang:
Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA. 168-173 - Shouliang Guo, Chao Fang, Jun Lin, Zhongfeng Wang:
A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity. 174-179 - Chen Ding, Yuxiang Huan, Lirong Zheng, Zhuo Zou:
Dynamic Precision Multiplier For Deep Neural Network Accelerators. 180-184 - Md Farhadur Reza:
Deep Reinforcement Learning for Self-Configurable NoC. 185-190 - Ivan Miketic, Emre Salman:
Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration. 191-194 - Umamaheswara Rao Tida, Madhava Sarma Vemuri:
Efficient Metal Inter-Layer Via Utilization Strategies for Three-dimensional Integrated Circuits. 195-200 - Jinyu Xie, Wenbo Yin, Lingli Wang:
Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGA. 201-206 - Jia-Bao Gao, Jian Wang, Md Tanvir Arafin, Jin-Mei Lai:
FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs. 207-212 - Jhanani Thiagarajan, Arnab A. Purkayastha, Atul Patil, Hamed Tabkhi:
Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs. 213-218 - Augusto W. Hoppe, Jürgen Becker, Fernanda Lima Kastensmidt:
Fine Grained Control Flow Checking with Dedicated FPGA Monitors. 219-224 - Renyuan Zhang, Tati Erlina, Tinh Van Nguyen, Yasuhiko Nakashima:
Hybrid Stochastic Computing Circuits in Continuous Statistics Domain. 225-230 - Yongjoon Ahn, Suhwan Kim, Hyunjoong Lee:
A Sub-1 ppm/°C CMOS Bandgap Voltage Reference With Process Tolerant Piecewise Second-Order Curvature Compensation. 231-235 - Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region. 236-241 - Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen:
Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. 242-247 - Shivam Bhasin, Trevor E. Carlson, Anupam Chattopadhyay, Vinay B. Y. Kumar, Avi Mendelson, Romain Poussier, Yaswanth Tavva:
Secure Your SoC: Building System-an-Chip Designs for Security. 248-253 - Vishant Gotra, Srinivasa Kodanda Rama Reddy:
Simultaneous Multi Voltage Aware Timing Analysis Methodology for SOC using Machine Learning. 254-257 - Vishant Gotra, Srinivasa Kodanda Rama Reddy, Tanniru Srinivasa Rao, Pavithra P:
Optimized Power Grid Planning for Enabling Low Power Features for Leakage Power Reduction in SOC. 258-261 - Ali Tariq, Howard Yang:
ASIC Power Estimation Across Revisions using Machine Learning. 262-264 - Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala:
AutoML for Multilayer Perceptron and FPGA Co-design. 265-266 - Sai Nimmalapudi, Harvey Stiegler, Andrew Marshall, Keith Jarreau:
Programmable Voltage Reference Circuit Using an Analog Floating Gate Device. 267-270 - Chia-Chun Lin, Kit Seng Tam, Chana-Cheng Ko, Hsin-Ping Yen, Shenz-Hsiu Wei, Yung-Chih Chen, Chun-Yao Wang:
A Dynamic Expansion Order Algorithm for the SAT-based Minimization. 271-276 - M. D. Arafat Kabir, Yarui Peng:
Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study. 277-282 - Mong Tee Sim, Yanyan Zhuang:
A SpaceWire PHY with Double Data Rate and Fallback Redundancy. 283-288
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