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ORCIDNirmal R. Saxena
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2020 – today
- 2024
[c26]Saurabh Hukerikar, Atieh Lotfi, Yanxiang Huang, Jason Campbell, Nirmal R. Saxena:
Optimizing Large-Scale Fault Injection Experiments through Martingale Hypothesis: A Systematic Approach for Reliability Assessment of Safety-Critical Systems. DSN-S 2024: 111-117- 2022
- [j20]Michael B. Sullivan
, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler:
Characterizing and Mitigating Soft Errors in GPU DRAM. IEEE Micro 42(4): 69-77 (2022) - [c25]Nirmal R. Saxena, Atieh Lotfi:
Error Model (EM) - A New Way of Doing Fault Simulation. ITC 2022: 324-333 - [c24]Saurabh Hukerikar, Nirmal R. Saxena:
Runtime Fault Diagnostics for GPU Tensor Cores. ITC 2022: 524-528 - 2021
- [c23]Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler:
Characterizing and Mitigating Soft Errors in GPU DRAM. MICRO 2021: 641-653 - 2020
- [c22]Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas:
On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors. ITC 2020: 1-10
2010 – 2019
- 2019
- [c21]Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang:
Resiliency of automotive object detection networks on GPU architectures. ITC 2019: 1-9 - 2018
- [c20]Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani:
Low Overhead Tag Error Mitigation for GPU Architectures. DSN 2018: 314-321 - [c19]Nirmal R. Saxena, Sanu Mathew, Krishna Saraswat:
Keynote 1: The road to resilient computing in autonomous driving is paved with redundancy. IRPS 2018: 1-3
2000 – 2009
- 2008
- [c18]François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh:
How Many Test Patterns are Useless? VTS 2008: 23-28 - 2004
- [j19]Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey:
Reconfigurable Architecture for Autonomous Self-Repair. IEEE Des. Test Comput. 21(3): 228-240 (2004) - [j18]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Efficient Design Diversity Estimation for Combinational Circuits. IEEE Trans. Computers 53(11): 1483-1492 (2004) - 2002
- [j17]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
A Design Diversity Metric and Analysis of Redundant Systems. IEEE Trans. Computers 51(5): 498-510 (2002) - 2001
- [c17]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Techniques for Estimation of Design Diversity for Combinational Logic Circuits. DSN 2001: 25-36 - 2000
- [j16]Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey:
Dependable Computing and Online Testing in Adaptive and Configurable Systems. IEEE Des. Test Comput. 17(1): 29-41 (2000) - [j15]Philip P. Shirvani, Nirmal R. Saxena, Edward J. McCluskey:
Software-implemented EDAC protection against SEUs. IEEE Trans. Reliab. 49(3): 273-284 (2000) - [j14]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Common-mode failures in redundant VLSI systems: a survey. IEEE Trans. Reliab. 49(3): 285-295 (2000) - [c16]Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey:
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. FCCM 2000: 175-184 - [c15]Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey:
A Reliable LZ Data Compressor on Reconfigurable Coprocessors. FCCM 2000: 249-258 - [c14]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Fault Escapes in Duplex Systems. VTS 2000: 453-458
1990 – 1999
- 1999
- [c13]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
A design diversity metric and reliability analysis for redundant systems. ITC 1999: 662-671 - [c12]Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey:
Finite state machine synthesis with concurrent error detection. ITC 1999: 672-679 - 1998
- [c11]Nirmal R. Saxena, Edward J. McCluskey:
Dependable adaptive computing systems-the ROAR project. SMC 1998: 2172-2177 - 1997
- [j13]Nirmal R. Saxena, Edward J. McCluskey:
Parallel Signatur Analysis Design with Bounds on Aliasing. IEEE Trans. Computers 46(4): 425-438 (1997) - 1996
- [j12]Nirmal R. Saxena, Edward J. McCluskey:
Counting Two-State Transition-Tour Sequences. IEEE Trans. Computers 45(11): 1337-1342 (1996) - [c10]Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li:
Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. ITC 1996: 904-913 - 1995
- [j11]Nirmal R. Saxena, David Chih-Wei Chang, Kevin Dawallu, Jaspal Kohli, Pat Helland:
Fault-Tolerant Features in the HaL Memory Management Unit. IEEE Trans. Computers 44(2): 170-180 (1995) - [j10]Daniel Boley, Gene H. Golub, Samy Makar, Nirmal R. Saxena, Edward J. McCluskey:
Floating Point Fault Tolerance with Backward Error Assertions. IEEE Trans. Computers 44(2): 302-311 (1995) - [c9]Nirmal R. Saxena, Chien Chen, Ravi Swami, Hideki Osone, Shalesh Thusoo, David Lyon, David Chang, Anand Dharmaraj, Niteen Patkar, Yizhi Lu, Ben Chia:
Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System. FTCS 1995: 464-471 - [c8]Babu Turumella, Aiman Kabakibo, Manjunath Bogadi, Karakunakara Menon, Shaleah Thusoo, Long Nguyen, Nirmal R. Saxena, Michael Chow:
Design Verification of a Super-Scalar RISC Processor. FTCS 1995: 472-477 - [c7]David R. Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal R. Saxena, Rolland Crunk:
HALSIM - A Very Fast SPARC-V9 Behavioral Model. MASCOTS 1995: 249-252 - 1994
- [j9]David R. Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal R. Saxena, Rolland Crunk:
HALSIM - a very fast SPARC V9 behavioral model. SIGARCH Comput. Archit. News 22(1): 52-58 (1994) - [j8]Nirmal R. Saxena, Edward J. McCluskey:
Linear Complexity Assertions for Sorting. IEEE Trans. Software Eng. 20(6): 424-431 (1994) - 1993
- [c6]Nirmal R. Saxena, Ravi Tangirala, Ajay Srivastava:
Algorithmic Synthesis of High Level Tests for Data Path Designs. FTCS 1993: 360-369 - [c5]David Chih-Wei Chang, Nirmal R. Saxena:
Concurrent Error Detection/Correction in the HAL MMU Chip. FTCS 1993: 630-635 - 1992
- [j7]Nirmal R. Saxena, Piero Franco, Edward J. McCluskey:
Simple Bounds on Serial Signature Analysis Aliasing for Random Testing. IEEE Trans. Computers 41(5): 638-645 (1992) - 1991
- [c4]Nirmal R. Saxena, Piero Franco, Edward J. McCluskey:
Bounds on Signature Analysis Aliasing for Random Testing. FTCS 1991: 104-113 - [c3]Nirmal R. Saxena, Piero Franco, Edward J. McCluskey:
Refined Bounds on Signature Analysis Aliasing for Random Testing. ITC 1991: 818-827 - 1990
- [j6]Nirmal R. Saxena, Edward J. McCluskey:
Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums. IEEE Trans. Computers 39(4): 554-559 (1990) - [j5]Nirmal R. Saxena, Edward J. McCluskey:
Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks. IEEE Trans. Computers 39(7): 969-975 (1990)
1980 – 1989
- 1989
- [c2]Nirmal R. Saxena, Edward J. McCluskey:
Control-flow checking using watchdog assists and extended-precision checksums. FTCS 1989: 428-435 - [c1]Nirmal R. Saxena, Edward J. McCluskey:
Arithmetic and galois checksums. ICCAD 1989: 570-573 - 1988
- [j4]John P. Robinson, Nirmal R. Saxena:
Simultaneous signature and syndrome compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(5): 584-589 (1988) - [j3]Nirmal R. Saxena, John P. Robinson:
Syndrome and transition count are uncorrelated. IEEE Trans. Inf. Theory 34(1): 64-69 (1988) - 1987
- [j2]John P. Robinson, Nirmal R. Saxena:
A Unified View of Test Compression Methods. IEEE Trans. Computers 36(1): 94-99 (1987) - 1986
- [j1]Nirmal R. Saxena, John P. Robinson:
Accumulator Compression Testing. IEEE Trans. Computers 35(4): 317-321 (1986)
Coauthor Index
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