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ORCIDAshok K. Saxena
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Journal Articles
- 2016
[j12]Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta:
Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. Microelectron. J. 55: 19-25 (2016)- 2012
- [j11]Surendra S. Rathod
, Ashok K. Saxena, Sudeb Dasgupta:
Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients. IET Circuits Devices Syst. 6(4): 218-226 (2012) - [j10]Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta:
Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity. J. Circuits Syst. Comput. 21(4) (2012) - [j9]Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta:
Impact of dual-k spacer on analog performance of underlap FinFET. Microelectron. J. 43(11): 883-887 (2012) - 2011
- [j8]Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta:
Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact. IET Circuits Devices Syst. 5(1): 52-58 (2011) - [j7]Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta:
Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology. J. Low Power Electron. 7(2): 163-171 (2011) - [j6]Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta:
Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation. Microelectron. J. 42(1): 165-172 (2011) - [j5]Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta:
Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET. Microelectron. J. 42(5): 688-692 (2011) - [j4]Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta:
A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier. Microelectron. Reliab. 51(4): 773-780 (2011) - 2010
- [j3]Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta:
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control. J. Low Power Electron. 6(4): 533-544 (2010) - [j2]Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta:
A proposed DG-FinFET based SRAM cell design with RadHard capabilities. Microelectron. Reliab. 50(8): 1181-1188 (2010) - 2009
- [j1]Y. K. Sudharshan, D. Sreenu, Ashok K. Saxena, Sudeb Dasgupta:
Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study. J. Low Power Electron. 5(1): 40-49 (2009)
Conference and Workshop Papers
- 2012
- [c4]Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta:
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET. VDAT 2012: 46-51 - 2011
- [c3]Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta:
Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach. SocProS (2) 2011: 365-375 - 2010
- [c2]Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta:
Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach. EMS 2010: 526-530 - 2009
- [c1]Patanjali Prakash, Ashok Kumar Saxena:
Design of Low Power High Speed ALU Using Feedback Switch Logic. ARTCom 2009: 899-902
Coauthor Index
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