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2020 – today
- 2024
[j30]Gianpiero Cabodi
, Paolo E. Camurati, Marco Palena, Paolo Pasini:
Improving Bounded Model Checking Exploiting Interpolation-Based Learning and Strengthening. IEEE Access 12: 119341-119349 (2024)- [j29]Gianpiero Cabodi, Paolo E. Camurati, Marco Palena, Paolo Pasini:
Hardware Model Checking Algorithms and Techniques. Algorithms 17(6): 253 (2024) - [j28]Gianpiero Cabodi, Paolo E. Camurati, João Marques-Silva, Marco Palena, Paolo Pasini:
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3083-3087 (2024) - 2022
- [j27]Gianpiero Cabodi, Paolo E. Camurati, Marco Palena, Paolo Pasini:
Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking. Formal Methods Syst. Des. 60(2): 117-146 (2022) - 2021
- [c51]Gianpiero Cabodi, Paolo E. Camurati, Alexey Ignatiev, João Marques-Silva, Marco Palena, Paolo Pasini:
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification. DATE 2021: 1122-1125 - 2020
- [j26]Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto:
Reducing Interpolant Circuit Size Through SAT-Based Weakening. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1524-1531 (2020)
2010 – 2019
- 2019
- [j25]Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto:
Logic Synthesis for Interpolant Circuit Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 380-384 (2019) - [c50]Gianpiero Cabodi, Paolo Camurati, Fabrizio F. Finocchiaro, Danilo Vendraminetto:
Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification. C2SI 2019: 462-479 - [c49]Edoardo Fadda, Daniele Manerba, Roberto Tadei, Paolo Camurati, Gianpiero Cabodi:
KPIs for Optimal Location of charging stations for Electric Vehicles: the Biella case-study. FedCSIS 2019: 123-126 - 2018
- [j24]Gianpiero Cabodi, Paolo Camurati, Carmelo Loiacono, Marco Palena, Paolo Pasini, Denis Patti, Stefano Quer:
To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking. Int. J. Softw. Tools Technol. Transf. 20(3): 313-325 (2018) - 2017
- [j23]Gianpiero Cabodi, Paolo Camurati, Sebastiano F. Finocchiaro, Francesco Savarese, Danilo Vendraminetto:
Embedded Systems Secure Path Verification at the Hardware/Software Interface. IEEE Des. Test 34(5): 38-46 (2017) - [j22]Gianpiero Cabodi, Paolo Camurati, Alan Mishchenko, Marco Palena, Paolo Pasini:
SAT solver management strategies in IC3: an experimental approach. Formal Methods Syst. Des. 50(1): 39-74 (2017) - [c48]Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto:
Interpolation-Based Learning as a Mean to Speed-Up Bounded Model Checking (Short Paper). SEFM 2017: 382-387 - 2016
- [j21]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
A graph-labeling approach for efficient cone-of-influence computation in model-checking problems with multiple properties. Softw. Pract. Exp. 46(4): 493-511 (2016) - [c47]Nicolas Boria, Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Stefano Quer:
A 7/2-Approximation Algorithm for the Maximum Duo-Preservation String Mapping Problem. CPM 2016: 11:1-11:8 - [c46]Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto:
Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. FMCAD 2016: 25-32 - [c45]Gianpiero Cabodi, Paolo Camurati, Sebastiano F. Finocchiaro, Carmelo Loiacono, Francesco Savarese, Danilo Vendraminetto:
Secure Path Verification. IVSW 2016: 1-6 - [i1]Nicolas Boria, Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Stefano Quer:
A Greedy Approach to Answer Reachability Queries on DAGs. CoRR abs/1611.02506 (2016)
2000 – 2009
- 2009
- [c44]Gianpiero Cabodi, Paolo Camurati, Luz Amanda Garcia, Marco Murciano, Sergio Nocco, Stefano Quer:
Speeding up model checking by exploiting explicit and hidden verification constraints. DATE 2009: 1686-1691 - 2008
- [c43]Gianpiero Cabodi, Paolo Camurati, Luz Amanda Garcia, Marco Murciano, Sergio Nocco, Stefano Quer:
Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking. FMCAD 2008: 1-8 - [c42]Gianpiero Cabodi, Paolo Camurati, Marco Murciano:
Automated abstraction by incremental refinement in interpolant-based model checking. ICCAD 2008: 129-136 - 2002
- [c41]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Can BDDs compete with SAT solvers on bounded model checking? DAC 2002: 117-122 - [c40]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Dynamic Scheduling and Clustering in Symbolic Image Computation. DATE 2002: 150-156 - 2001
- [j20]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring. J. Syst. Archit. 47(2): 163-179 (2001) - [c39]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Biasing symbolic search by means of dynamic activity profiles. DATE 2001: 9-15 - 2000
- [j19]Stefano Quer, Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Ellen Sentovich, Robert K. Brayton:
Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks. Formal Methods Syst. Des. 17(2): 107-134 (2000) - [j18]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Symbolic forward/backward traversals of large finite state machines. J. Syst. Archit. 46(12): 1137-1158 (2000) - [j17]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Improving symbolic reachability analysis by means of activityprofiles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1065-1075 (2000)
1990 – 1999
- 1999
- [j16]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Improving the efficiency of BDD-based operators by means of partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 545-556 (1999) - [c38]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Improving Symbolic Traversals by Means of Activity Profiles. DAC 1999: 306-311 - [c37]Gianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer:
Computing Timed Transition Relations for Sequential Cycle-Based Simulation. DATE 1999: 8-12 - 1998
- [j15]Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
The General Product Machine: a New Model for Symbolic FSM Traversal. Formal Methods Syst. Des. 12(3): 267-289 (1998) - [j14]Gianpiero Cabodi, Stefano Quer, Paolo Camurati:
Memory Optimization in Function and Set Manipulation with BDDs. Softw. Pract. Exp. 28(1): 99-120 (1998) - [j13]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Auxiliary variables for BDD-based representation and manipulation of Boolean functions. ACM Trans. Design Autom. Electr. Syst. 3(3): 309-340 (1998) - 1997
- [j12]Gianpiero Cabodi, Paolo Camurati:
Symbolic FSM traversals based on the transition relation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 448-457 (1997) - [c36]Gianpiero Cabodi, Paolo Camurati, Antonio Lioy, Massimo Poncino, Stefano Quer:
A parallel approach to symbolic traversal based on set partitioning. CHARME 1997: 167-184 - [c35]Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer:
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. DAC 1997: 728-733 - [c34]Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer:
Verification and synthesis of counters based on symbolic techniques. ED&TC 1997: 176-181 - 1996
- [c33]Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich:
Incremental re-encoding for symbolic traversal of product machines. EURO-DAC 1996: 158-163 - [c32]Stefano Quer, Gianpiero Cabodi, Paolo Camurati:
Decomposed symbolic forward traversals of large finite state machines. EURO-DAC 1996: 170-175 - [c31]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Improved reachability analysis of large finite state machines. ICCAD 1996: 354-360 - [c30]Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovich:
Enhancing FSM Traversal by Temporary Re-Encoding. ICCD 1996: 6-11 - 1995
- [j11]Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina:
Industrial BIST of Embedded RAMs. IEEE Des. Test Comput. 12(3): 86-95 (1995) - [c29]Gianpiero Cabodi, Stefano Quer, Paolo Camurati:
Transforming boolean relations by symbolic encoding. CHARME 1995: 161-170 - [c28]Gianpiero Cabodi, Stefano Quer, Paolo Camurati:
Computing subsets of equivalence classes for large FSMs. EURO-DAC 1995: 288-293 - [e1]Paolo Camurati, Hans Eveking:
Correct Hardware Design and Verification Methods, IFIP WG 10.5 Advanced Research Working Conference, CHARME '95, Frankfurt/Main, Germany, October 2-4, 1995, Proceedings. Lecture Notes in Computer Science 987, Springer 1995, ISBN 3-540-60385-9 [contents] - 1994
- [c27]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths. DAC 1994: 289-293 - [c26]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Symbolic exploration of large circuits with enhanced forward/backward traversals. EURO-DAC 1994: 22-27 - [c25]Paolo Camurati, Fulvio Corno, Paolo Prinetto, Catherine Bayol, Bernard Soulas:
System-Level Modeling and Verification: a Comprehensive Design Methodology. EDAC-ETC-EUROASIC 1994: 636-640 - [c24]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Symbolic traversals of data paths with auxiliary variables. Great Lakes Symposium on VLSI 1994: 93-96 - [c23]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Efficient State Space Pruning in Symbolic Backward Traversal. ICCD 1994: 230-235 - [c22]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Detecting hard faults with combined approximate forward/backward symbolic techniques. ISCAS 1994: 299-302 - [c21]Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Full-Symbolic ATPG for Large Circuits. ITC 1994: 980-988 - [c20]Paolo Camurati, Fulvio Corno, Michela Meo, Paolo Prinetto:
A new functional fault model for system-level descriptions. VTS 1994: 214-219 - [c19]Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina:
An industrial experience in the built-in self test of embedded RAMs. VTS 1994: 306-311 - 1993
- [j10]Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
An approach to sequential circuit diagnosis based on formal verification techniques. J. Electron. Test. 4(1): 11-17 (1993) - [c18]Paolo Camurati, Fulvio Corno, Paolo Prinetto:
A Methodology for System-Level Design for Verifiability. CHARME 1993: 80-91 - [c17]Gianpiero Cabodi, Paolo Camurati:
Advancements in Symbolic Traversal Technique. CHARME 1993: 155-166 - [c16]Paolo Camurati, Fulvio Corno, Paolo Prinetto:
Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation. CHDL 1993: 31-44 - [c15]Paolo Camurati, Fulvio Corno, Paolo Prinetto:
An efficient tool for system-level verification of behaviors and temporal properties. EURO-DAC 1993: 124-129 - [c14]Gianpiero Cabodi, Paolo Camurati:
Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation. ICCD 1993: 299-303 - 1992
- [c13]Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda:
A New Model for Improving symbolic Product Machine Traversal. DAC 1992: 614-619 - [c12]Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Cross-fertilizing FSM verification techniques and sequential diagnosis. EURO-DAC 1992: 306-311 - [c11]Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Sequential Circuit Diagnosis Based on Formal Verification Techniques. ITC 1992: 187-196 - [c10]Paolo Camurati, Fulvio Corno, Fulvio Prinetto, Matteo Sonza Reorda:
A simulation-based approach to test pattern generation for synchronous sequential circuits. VTS 1992: 263-267 - 1991
- [j9]Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda:
TPDL: Extended Temporal Profile Description Language. Softw. Pract. Exp. 21(4): 355-374 (1991) - [c9]Paolo Camurati, Tiziana Margaria, Paolo Prinetto:
Resolution-based correctness proofs of synchronous circuits. EURO-DAC 1991: 11-15 - [c8]Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda:
Proving finite state machines correct with an automaton-based method. Great Lakes Symposium on VLSI 1991: 255-258 - 1990
- [j8]Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda:
Exact probabilistic testability measures for multi-output circuits. J. Electron. Test. 1(3): 229-234 (1990) - [j7]Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda:
Assessing the diagnostic power of test pattern sets. Microprocessing and Microprogramming 30(1-5): 413-419 (1990) - [j6]Paolo Camurati, Tiziana Margaria, Paolo Prinetto:
The OTTER environment for resolution-based proof of hardware correctness. Microprocessing and Microprogramming 30(1-5): 421-428 (1990) - [c7]Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda:
The Use of Model Checking in ATPG for Sequential Circuits. CAV 1990: 86-95 - [c6]Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda:
Model Checking and Graph Theory in Sequential ATPG. CAV (DIMACS/AMS volume) 1990: 505-518 - [c5]Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda:
Diagnosis oriented test pattern generation. EURO-DAC 1990: 470-474 - [c4]Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda:
A diagnostic test pattern generation algorithm. ITC 1990: 52-58
1980 – 1989
- 1989
- [j5]Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda:
Expressing logical and temporal conditions in simulation environments: TPDL*. Microprocessing and Microprogramming 26(4): 241-252 (1989) - [j4]Paolo Camurati, Tiziana Margaria, Paolo Prinetto:
Systolic array description in F2. Microprocessing and Microprogramming 27(1-5): 171-178 (1989) - [j3]Paolo Camurati, Marco Mezzalama, Paolo Prinetto:
Knowledge-based systems as an aid to computer-aided repair. Microprocess. Microsystems 13(7): 457-461 (1989) - 1988
- [j2]Paolo Camurati, Paolo Prinetto:
Formal Verification of Hardware Correctness: Introduction and Survey of Current Research. Computer 21(7): 8-19 (1988) - [j1]Paolo Camurati, Paolo Gianoglio, Renato Gianoglio, Paolo Prinetto:
ESTA: an expert system for DFT rule verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(11): 1172-1180 (1988) - [c3]Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda:
Random testability analysis: comparing and evaluating existing approaches. ICCD 1988: 70-73 - [c2]Dominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto:
A functional approach to formal hardware verification: the MTI experience. ICCD 1988: 592-595 - 1986
- [c1]Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto:
Experiences in Prolog-Based DFT Rule Checking. FJCC 1986: 909-914
Coauthor Index
[j30] [j29] [j28] [j27] [c51] [j26] [j25] [c50] [c49] [j24] [j23] [j22] [c48] [j21] [c47] [c46] [c45] [i1] [c44] [c43] [c42] [c41] [c40] [j20] [c39] [j19] [j18] [j17] [j16] [c38] [c37] [j15] [j14] [j13] [j12] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c24] [c23] [c22] [c21] [j10] [c17] [c14] [c13] [c12] [c11] [j9] [j5] [c1]
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