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2010 – 2019
- 2017
[c8]Adeboye Stephen Oyeniran
, Artjom Jasnetski, Anton Tsertov, Raimund Ubar:
High-level test data generation for software-based self-test in microprocessors. MECO 2017: 1-6- [c7]Artjom Jasnetski, Raimund Ubar, Anton Tsertov:
Automated software-based self-test generation for microprocessors. MIXDES 2017: 453-458 - 2016
- [c6]Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schölzel, Raimund Ubar:
High-level modeling and testing of multiple control faults in digital systems. DDECS 2016: 144-149 - [c5]Artjom Jasnetski, Raimund Ubar, Anton Tsertov:
On automatic software-based self-test program generation based on high-level decision diagrams. LATS 2016: 177 - 2015
- [c4]Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar:
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS 2015: 251-254 - 2014
- [c3]Artjom Jasnetski, Raimund Ubar, Anton Tsertov, Helena Kruus:
Laboratory framework TEAM for investigating the dependability issues of microprocessor systems. EWME 2014: 80-83 - [c2]Raimund Ubar, Anton Tsertov, Artjom Jasnetski, Marina Brik:
Software-based self-test generation for microprocessors with high-level decision diagrams. LATW 2014: 1-6 - 2013
- [c1]Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski:
On in-system programming of non-volatile memories. MIXDES 2013: 408-413
Coauthor Index
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