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2010 – 2019
- 2016
[j6]Hanwool Jeong
, Juhyun Park, Tae Woo Oh, Woojin Rim, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1059-1063 (2016)- [c4]Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyu-Hong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, E. S. Jung, Steve Sungho Park, Kinam Kim:
17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. ISSCC 2016: 306-307 - 2015
- [j5]Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang, Jaeho Park, Sunghyun Park, Yongho Kim, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyu-Hong Kim, Jintae Kim, Young-Keun Lee, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi, Hyo-Sig Won, Jaehong Park:
A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. IEEE J. Solid State Circuits 50(1): 158-169 (2015) - [j4]Hanwool Jeong, Taewon Kim, Younghwi Yang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1062-1070 (2015) - [j3]Hanwool Jeong, Taewon Kim, Kyoman Kang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1555-1563 (2015) - [j2]Hanwool Jeong, Taewon Kim, Taejoong Song, Gyu-Hong Kim, Seong-Ook Jung:
Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1370-1374 (2015) - [c3]Byung-Jun Jang, Chan-Ho Lee, Sung-Hun Sim, Kyu-Won Choi, Do-Hun Byun, Yeon-Ho Jung, Ki-Man Park, Dong-Yeon Heo, Gyu-Hong Kim, Joon-Sung Yang:
Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield. ISCAS 2015: 2541-2544 - 2014
- [c2]Hanwool Jeong, Taewon Kim, Seong-Ook Jung, Taejoong Song, Gyu-Hong Kim:
Pseudo NMOS based sense amplifier for high speed single-ended SRAM. ICECS 2014: 331-334 - [c1]Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang, Jaeho Park, Sunghyun Park, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyu-Hong Kim, Jintae Kim, Young-Keun Lee, Kee Sup Kim, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi:
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications. ISSCC 2014: 232-233
2000 – 2009
- 2005
- [j1]Myoung-Kyu Seo, Soung-Hoon Sim, Myoung-Hee Oh, Hyo-Sang Lee, Sang-Won Kim, In-Wook Cho, Gyu-Hong Kim, Moon-Gone Kim:
A 130-nm 0.9-V 66-MHz 8-Mb (256K × 32) local SONOS embedded flash EEPROM. IEEE J. Solid State Circuits 40(4): 877-883 (2005)
Coauthor Index
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