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ORCIDEddie Hung
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2020 – today
- 2024
[c25]Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne:
DynaRapid: Fast-Tracking from C to Routed Circuits. FPL 2024: 24-32- 2023
- [j9]Licheng Guo
, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16(4): 59:1-59:30 (2023) - [c24]Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek:
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE 2023: 1-6 - [c23]Chris Lavin, Eddie Hung:
Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling. ICCAD 2023: 1-7 - 2022
- [c22]Hossein Omidian, Eddie Hung, Dinesh Gaitonde:
100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. ARC 2022: 1-16
2010 – 2019
- 2019
- [c21]David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic:
Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. FCCM 2019: 1-4 - [c20]Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung:
EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation. FCCM 2019: 5-8 - [i2]David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic:
Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. CoRR abs/1903.10407 (2019) - 2018
- [j8]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 2:1-2:22 (2018) - [c19]Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton:
Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. ETS 2018: 1-2 - [c18]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL 2018: 4:1 - 2017
- [j7]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34(6): 36-45 (2017) - [j6]Eddie Hung, Tim Todman, Wayne Luk:
Transparent In-Circuit Assertions for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1193-1202 (2017) - [c17]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
STRIPE: Signal selection for runtime power estimation. FPL 2017: 1-8 - 2016
- [c16]Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM 2016: 56-63 - [c15]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA 2016: 276 - [i1]Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton:
Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. CoRR abs/1606.06457 (2016) - 2015
- [c14]Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk:
Accelerating SpMV on FPGAs by Compressing Nonzero Values. FCCM 2015: 64-67 - [c13]Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk:
Delay-Bounded Routing for Shadow Registers. FPGA 2015: 56-65 - [c12]Eddie Hung:
Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry. FPL 2015: 1-4 - 2014
- [j5]Eddie Hung, Steven J. E. Wilton:
Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. ACM Trans. Design Autom. Electr. Syst. 19(2): 14:1-14:23 (2014) - [j4]Eddie Hung, Steven J. E. Wilton:
Incremental Trace-Buffer Insertion for FPGA Debug. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 850-863 (2014) - [c11]Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton:
Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. ARC 2014: 73-84 - [c10]Eddie Hung, Tim Todman, Wayne Luk:
Transparent insertion of latency-oblivious logic onto FPGAs. FPL 2014: 1-8 - 2013
- [j3]Eddie Hung, Bradley R. Quinton, Steven J. E. Wilton:
Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. IEEE Des. Test 30(4): 8-15 (2013) - [j2]Eddie Hung, Steven J. E. Wilton:
Scalable Signal Selection for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1103-1115 (2013) - [c9]Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton:
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. FCCM 2013: 45-52 - [c8]Eddie Hung, Steven J. E. Wilton:
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. FPGA 2013: 19-28 - [c7]Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton:
Maximum flow algorithms for maximum observability during FPGA debug. FPT 2013: 20-27 - 2012
- [j1]José Luis Núñez-Yáñez, Atukem Nabina, Eddie Hung, George Vafiadis:
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 437-448 (2012) - [c6]Eddie Hung, Steven J. E. Wilton:
Limitations of incremental signal-tracing for FPGA debug. FPL 2012: 49-56 - [c5]Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung:
Rapid RTL-based signal ranking for FPGA prototyping. FPT 2012: 1-7 - 2011
- [c4]Eddie Hung, Steven J. E. Wilton:
Speculative Debug Insertion for FPGAs. FPL 2011: 524-531 - [c3]Eddie Hung, Steven J. E. Wilton:
On evaluating signal selection algorithms for post-silicon debug. ISQED 2011: 290-296
2000 – 2009
- 2009
- [c2]Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong:
A detailed delay path model for FPGAs. FPT 2009: 96-103 - 2008
- [c1]José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras:
A configurable and programmable motion estimation processor for the H.264 video codec. FPL 2008: 149-154
Coauthor Index
aka: Steven J. E. Wilton
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