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ORCIDPankaj Pant
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2020 – today
- 2023
[c13]Arani Sinha, Glenn Colón-Bonet, Michael Fahy, Pankaj Pant, Haijing Mao, Akhilesh Shukla:
Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure. ITC 2023: 56-59- 2020
- [c12]Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant:
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. ITC 2020: 1-10
2010 – 2019
- 2016
- [c11]Dilip Bhavsar, Michael Lohmiller, Pankaj Pant:
Lateral coupling faults in multi-ported register files and methods for their testing. VTS 2016: 1-6 - 2011
- [c10]Pankaj Pant, Eric Skeels:
Hardware hooks for transition scan characterization. ITC 2011: 1-8 - 2010
- [c9]Pankaj Pant, Joshua Zelman, Glenn Colón-Bonet, Jennifer Flint, Steve Yurash:
Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor. ITC 2010: 526-535
2000 – 2009
- 2009
- [c8]Rex Petersen, Pankaj Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson:
Voltage transient detection and induction for debug and test. ITC 2009: 1-10 - [c7]Pankaj Pant, Joshua Zelman:
Understanding Power Supply Droop during At-Speed Scan Testing. VTS 2009: 227-232 - 2002
- [j2]Mondira Deb Pant, Pankaj Pant, D. Scott Wills:
On-chip decoupling capacitor optimization using architectural level prediction. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 319-326 (2002) - 2001
- [j1]Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee:
Path delay fault diagnosis in combinational circuits with implicitfault enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10): 1226-1235 (2001) - 2000
- [c6]Pankaj Pant, Abhijit Chatterjee:
Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application. ITC 2000: 245-252 - [c5]Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari:
Inductive Noise Reduction at the Architectural Level. VLSI Design 2000: 162-167
1990 – 1999
- 1999
- [c4]Pankaj Pant, Abhijit Chatterjee:
Efficient diagnosis of path delay faults in digital logic circuits. ICCAD 1999: 471-476 - [c3]Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari:
An architectural solution for the inductive noise problem due to clock-gating. ISLPED 1999: 255-257 - 1997
- [c2]Pankaj Pant, Vivek De, Abhijit Chatterjee:
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. DAC 1997: 403-408 - 1996
- [c1]Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham:
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. VTS 1996: 354-361
Coauthor Index
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