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ORCIDSung-Yun Park
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2020 – today
- 2024
[c7]Sungjin Oh, Hyunsoo Song, Jose Roberto Lopez Ruiz, Wangbo Chen, Sung-Yun Park, Michael P. Flynn, Euisik Yoon:
A 79.2dB-SNDR Slope-Adaptive Dynamic Zoom-and-Track Incremental sΔΔ Neural Recording Frontend with Resolution-Preservative 192mV/ms Transient Tracking. VLSI Technology and Circuits 2024: 1-2- 2023
- [j7]Sungjin Oh
, Hyunsoo Song, Nathan Slager, Jose Roberto Lopez Ruiz, Sung-Yun Park, Euisik Yoon:
Power-Efficient LFP-Adaptive Dynamic Zoom-and-Track Incremental ΔΣ Front-End for Dual-Band Subcortical Recordings. IEEE Trans. Biomed. Circuits Syst. 17(4): 741-753 (2023) - [c6]Sung-Yun Park, Seung-Jin Hong, Sang-Kwang Lee:
Human Interactive Learning with Intrinsic Reward. CoG 2023: 1-4 - 2022
- [j6]Yu-Ju Lin, Hyunsoo Song, Sungjin Oh, Mihály Vöröslakos, Kanghwan Kim, Xing Chen, David D. Wentzloff, György Buzsáki, Sung-Yun Park, Euisik Yoon:
A 3.1-5.2GHz, Energy-Efficient Single Antenna, Cancellation-Free, Bitwise Time-Division Duplex Transceiver for High Channel Count Optogenetic Neural Interface. IEEE Trans. Biomed. Circuits Syst. 16(1): 52-63 (2022) - [j5]Sung-Yun Park, Kyounghwan Na, Mihály Vöröslakos, Hyunsoo Song, Nathan Slager, Sungjin Oh, John P. Seymour, György Buzsáki, Euisik Yoon:
A Miniaturized 256-Channel Neural Recording Interface With Area-Efficient Hybrid Integration of Flexible Probes and CMOS Integrated Circuits. IEEE Trans. Biomed. Eng. 69(1): 334-346 (2022) - [c5]Sungjin Oh, Hyunsoo Song, Nathan Slager, Jose Roberto Lopez Ruiz, Sung-Yun Park, Euisik Yoon:
LFP-Adaptive Dynamic Zoom-and-Tracking Dual-Band Neural Recording Front-End Using a Power-Efficient Incremental Delta-Sigma ADC. BioCAS 2022: 75-79 - 2021
- [c4]Hyunsoo Song, Sungjin Oh, Juan Salinas, Sung-Yun Park, Euisik Yoon:
A 5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers. VLSI Circuits 2021: 1-2
2010 – 2019
- 2018
- [j4]Sung-Yun Park, Jihyun Cho, Kyounghwan Na, Euisik Yoon:
Modular 128-Channel Δ-ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems. IEEE J. Solid State Circuits 53(2): 501-514 (2018) - [j3]Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon:
Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals. IEEE J. Solid State Circuits 53(4): 1102-1114 (2018) - [j2]Sun-Il Chang, Sung-Yun Park, Euisik Yoon:
Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems. Sensors 18(1): 263 (2018) - [c3]Adam E. Mendrela, Sung-Yun Park, Mihály Vöröslakos, Michael P. Flynn, Euisik Yoon:
A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping. VLSI Circuits 2018: 125-126 - 2015
- [j1]Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon:
A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems. IEEE Trans. Biomed. Circuits Syst. 9(6): 885-895 (2015) - [c2]Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon:
12.3 PWM buck converter with >80% PCE in 45μA-to-4mA loads using analog-digital hybrid control for impiantale biomedical systems. ISSCC 2015: 1-3 - [c1]Sung-Yun Park, Jihyun Cho, Kyounghwan Na, Euisik Yoon:
Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ analog front-end architecture with 4.84fJ/C-s·mm2 energy-area product. VLSIC 2015: 112-
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