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2010 – 2019
- 2019
[j4]Chia-Wei Tseng, Po-Hao Lai, Bo-Sheng Huang, Li-Der Chou, Meng-Chiou Wu:
NFV deployment strategies in SDN network. Int. J. High Perform. Comput. Netw. 14(2): 237-248 (2019)
2000 – 2009
- 2008
- [j3]Meng-Chiou Wu, Rung-Bin Lin:
Finding Dicing Plans for Multiple Project wafers fabricated with Shuttle Mask. J. Circuits Syst. Comput. 17(1): 15-31 (2008) - [j2]Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai:
Chip placement in a reticle for multiple-project wafer fabrication. ACM Trans. Design Autom. Electr. Syst. 13(1): 22:1-22:21 (2008) - 2007
- [j1]Rung-Bin Lin, Meng-Chiou Wu, Shih-Cheng Tsai:
Reticle Design for Minimizing Multiproject Wafer Production Cost. IEEE Trans Autom. Sci. Eng. 4(4): 589-595 (2007) - [c7]Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu:
Reticle Exposure Plans for Multi-Project Wafers. DDECS 2007: 341-344 - 2006
- [c6]Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai:
Design space exploration for minimizing multi-project wafer production cost. ASP-DAC 2006: 783-788 - 2005
- [c5]Meng-Chiou Wu, Rung-Bin Lin:
Reticle floorplanning of flexible chips for multi-project wafers. ACM Great Lakes Symposium on VLSI 2005: 494-497 - [c4]Meng-Chiou Wu, Rung-Bin Lin:
Multiple project wafers for medium-volume IC production. ISCAS (5) 2005: 4725-4728 - [c3]Meng-Chiou Wu, Rung-Bin Lin:
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. ISQED 2005: 610-615 - [c2]Meng-Chiou Wu, Rung-Bin Lin:
A Comparative Study on Dicing of Multiple Project Wafers. ISVLSI 2005: 314-315
1990 – 1999
- 1998
- [c1]Rung-Bin Lin, Meng-Chiou Wu:
A New Statistical Approach to Timing Analysis of VLSI Circuits. VLSI Design 1998: 507-
Coauthor Index
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