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2020 – today
- 2024
[j6]Ben Perach
, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky:
Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. IEEE Trans. Emerg. Top. Comput. 12(1): 7-22 (2024)- 2023
- [j5]Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky:
ClaPIM: Scalable Sequence Classification Using Processing-in-Memory. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1347-1357 (2023) - [c6]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
On Consistency for Bulk-Bitwise Processing-in-Memory. HPCA 2023: 705-717 - [c5]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. NEWCAS 2023: 1-5 - [c4]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. SOCC 2023: 1-6 - [i9]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. CoRR abs/2302.01675 (2023) - [i8]Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky:
ClaPIM: Scalable Sequence CLAssification using Processing-In-Memory. CoRR abs/2302.08284 (2023) - [i7]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. CoRR abs/2307.00658 (2023) - [i6]Ben Perach, Shahar Kvatinsky:
An Asynchronous and Low-Power True Random Number Generator using STT-MTJ. CoRR abs/2307.14476 (2023) - 2022
- [j4]Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky:
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. ACM J. Emerg. Technol. Comput. Syst. 18(2): 43:1-43:29 (2022) - [i5]Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky:
PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. CoRR abs/2203.10486 (2022) - [i4]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
On Consistency for Bulk-Bitwise Processing-in-Memory. CoRR abs/2211.07542 (2022) - 2021
- [c3]Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. DAC 2021: 199-204 - [i3]Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. CoRR abs/2105.04212 (2021) - [i2]Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky:
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. CoRR abs/2107.10308 (2021) - 2020
- [c2]Ben Perach, Shahar Kvatinsky:
An Asynchronous and Low-Power True Random Number Generator using STT-MTJ. ISCAS 2020: 1
2010 – 2019
- 2019
- [j3]Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. IEEE Micro 39(1): 33-43 (2019) - [j2]Ben Perach, Shahar Kvatinsky:
An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2473-2484 (2019) - [c1]Ben Perach, Shahar Kvatinsky:
STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ. DATE 2019: 264-267 - [i1]Tzofnat Greenberg-Toledo, Ben Perach, Daniel Soudry, Shahar Kvatinsky:
MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks. CoRR abs/1912.12636 (2019) - 2018
- [j1]Ben Perach, Shlomo Weiss:
SiMT-DSP: A Massively Multithreaded DSP Architecture. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1413-1426 (2018)
Coauthor Index
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