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ORCIDSajjad Parvin
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2020 – today
- 2024
[c10]Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Hidden Cost of Circuit Design with RFETs. DATE 2024: 1-2- 2023
- [c9]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
:
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. ASP-DAC 2023: 683-689 - [c8]Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. COINS 2023: 1-4 - [c7]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. DATE 2023: 1-2 - [c6]Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. ISVLSI 2023: 1-6 - 2022
- [c5]Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. ASP-DAC 2022: 429-435 - 2021
- [c4]Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun:
Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. ISVLSI 2021: 402-405 - [c3]Sajjad Parvin, Mustafa Altun:
A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks. ISVLSI 2021: 406-411 - [i1]Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun:
Efficient Hardware Realizations of Feedforward Artificial Neural Networks. CoRR abs/2108.02073 (2021) - 2020
- [c2]Levent Aksoy, Sajjad Parvin, Mohammadreza Esmali Nojehdeh, Mustafa Altun:
Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j2]Sajjad Parvin, Mustafa Altun:
Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates. IEEE Access 7: 163939-163947 (2019) - [c1]Sajjad Parvin, Mustafa Altun:
Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates. IOLTS 2019: 64-67 - 2018
- [j1]Mustafa Altun, Sajjad Parvin, M. Hüsrev Cilasun:
Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits. IEEE Access 6: 74475-74484 (2018)
Coauthor Index
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last updated on 2024-10-01 21:38 CEST by the dblp team
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