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ORCIDRazieh Ghasemi
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2020 – today
- 2024
[j5]Razieh Ghasemi
, Mohammad Azim Karami:
A low phase noise quadrature VCO using super-harmonic coupling technique in 65-nm CMOS technology. Int. J. Circuit Theory Appl. 52(1): 97-110 (2024)- 2023
- [j4]Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri:
High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures. IEEE Embed. Syst. Lett. 15(1): 33-36 (2023) - [j3]Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri:
Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits. Frontiers Inf. Technol. Electron. Eng. 24(4): 599-616 (2023) - 2022
- [j2]Razieh Ghasemi, Mohammad Azim Karami:
A 10-bit 1GSample/s hybrid digital-to-analog converter with a modified thermometer decoder in 65-nm CMOS technology. Int. J. Circuit Theory Appl. 50(1): 83-107 (2022)
2010 – 2019
- 2019
- [j1]Hossein Ghasemian, Razieh Ghasemi, Ebrahim Abiri, Mohammad Reza Salehi:
A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology. Microelectron. J. 92 (2019)
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