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ORCIDTianxiang Wu
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2020 – today
- 2024
[c15]Tianxiang Wu, Han Chen, Luozheng Qin, Ziqiang Cao, Chunhui Ai:
Improving Copy-oriented Text Generation via EDU Copy Mechanism. LREC/COLING 2024: 8768-8780- [i1]Yu Xie, Qian Qiao, Jun Gao, Tianxiang Wu, Shaoyao Huang, Jiaqing Fan, Ziqiang Cao, Zili Wang, Yue Zhang, Jielei Zhang, Huyang Sun:
DNTextSpotter: Arbitrary-Shaped Scene Text Spotting via Improved Denoising Training. CoRR abs/2408.00355 (2024) - 2023
- [j10]Xi Wang, Dong Wei, Zhiyang Zhang, Tianxiang Wu, Xu Chen, Yong Chen
, Junyan Ren, Shunli Ma:
A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. Int. J. Circuit Theory Appl. 51(4): 1530-1547 (2023) - [c14]Xiaodi Feng, Shunli Ma, Muxi Zou, Tianxiang Wu:
A High Gain and Wide Bandwidth Dual-Power CMOS Op-amp for High-Speed ADCs Application. ASICON 2023: 1-4 - [c13]Cai Tian, Tianxiang Wu, Shunli Ma, Wenzhong Bao:
An Improved Delay Cell with Low Power Consumption and Strong Driving Capability. ASICON 2023: 1-4 - [c12]Yigang Wei, Tianxiang Wu, Shunli Ma, Junyan Ren:
A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS. ASICON 2023: 1-4 - [c11]Lei Wu, Junyan Ren, Tianxiang Wu, Shunli Ma:
A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs. ASICON 2023: 1-4 - [c10]Jing Yuan, Wenzhong Bao, Tianxiang Wu, Shunli Ma:
High Performance Bootstrap Switch for 14 bit SAR ADC with Redundancy in SMIC 180nm. ASICON 2023: 1-4 - [c9]Muxi Zou, Shunli Ma, Xiaodi Feng, Junyan Ren, Tianxiang Wu:
A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic. ASICON 2023: 1-4 - [c8]Lingwen Kong, Zheping Zhu, Liang Xu, Tianxiang Wu, Xiaolu Xu:
Neural Network-Based Financial Distress Prediction for Listed Companies in China. BDEIM 2023: 199-203 - 2022
- [j9]Tianxiang Wu, Yang Liu, Weidong Li:
Adaptive Cooperative Tracking Control of Multiple Trains With Uncertain Dynamics and External Disturbances Based on Adjacent Information. IEEE Access 10: 23677-23686 (2022) - [j8]Tianxiang Wu, Yang Liu, Shaohua Chen, He Wang, Haodong Chen:
Cooperative Neuro-Adaptive Fault-Tolerant Tracking Control for a Train Platoon Under Actuator Saturation. IEEE Access 10: 133803-133814 (2022) - [j7]Huajie Huang, Junjie Dai, Long Dou, Junfu Liu, Yunpeng Liu, Taotao Chen, Tianxiang Wu, Junhui Li:
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process. J. Electron. Test. 38(2): 195-203 (2022) - [j6]Tianxiang Wu, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma:
A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. Int. J. Circuit Theory Appl. 50(2): 367-381 (2022) - [j5]Zhiyang Zhang, Lihe Nie, Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma:
A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. Int. J. Circuit Theory Appl. 50(6): 1834-1854 (2022) - [c7]Wenyang Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen, Shunli Ma:
A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process. APCCAS 2022: 337-340 - 2021
- [j4]Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, Junyan Ren:
A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System. IEEE Access 9: 74752-74762 (2021) - [j3]Shunli Ma, Tianxiang Wu, Jincheng Zhang, Junyan Ren:
A 5G Wireless Event-Driven Sensor Chip for Online Power-Line Disturbances Detecting Network in 0.25 μm GaAs Process. IEEE Trans. Ind. Electron. 68(6): 5271-5280 (2021) - [c6]Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma:
A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. A-SSCC 2021: 1-3 - [c5]Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, Junyan Ren:
A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. ESSCIRC 2021: 195-198 - 2020
- [j2]Shunli Ma, Yan Wang, Xinyu Chen, Tianxiang Wu, Xi Wang, Hongwei Tang, Yuting Yao, Hao Yu, Yaochen Sheng, Jingyi Ma, Junyan Ren, Wenzhong Bao:
Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model. IEEE Access 8: 197287-197299 (2020) - [j1]Shunli Ma, Tianxiang Wu, Junyan Ren:
A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC. IEEE Access 8: 219695-219708 (2020)
2010 – 2019
- 2019
- [c4]Dong Wei, Jincheng Zhang, Tianxiang Wu, Shunli Ma, Junyan Ren:
A 22-40.5 GHz UWB LNA Design in 0.15um GaAs. ASICON 2019: 1-4 - [c3]Tianxiang Wu, Jincheng Zhang, Dong Wei, Lihe Nie, Yuting Yao, Shunli Ma, Junyan Ren:
A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication. ASICON 2019: 1-4 - [c2]Yuting Yao, Manxin Li, Tianxiang Wu, Hu Xu, Shunli Ma, Wenzhong Bao, Junyan Ren:
SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors. ASICON 2019: 1-4 - [c1]Jincheng Zhang, Lihe Nie, Dong Wei, Tianxiang Wu, Shunli Ma, Junyan Ren:
A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS. ASICON 2019: 1-4
Coauthor Index
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last updated on 2024-09-09 01:12 CEST by the dblp team
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