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ORCIDTaeik Kim
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2020 – today
- 2021
[c19]Jens Anders, Taeik Kim, David T. Blaauw:
Session 5 Overview: Analog Interfaces Analog Subcommittee. ISSCC 2021: 70-71- 2020
- [j5]Jeongho Hwang
, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong:
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1834-1838 (2020)
2010 – 2019
- 2019
- [c18]Xiaohua Huang, Kunnong Zeng, Yuguang Liu, Woogeun Rhee, Taeik Kim, Zhihua Wang:
A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL. CICC 2019: 1-4 - 2018
- [c17]Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong:
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. BCICTS 2018: 263-266 - [c16]Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hyung Jong Ko:
A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology. ISSCC 2018: 120-122 - [c15]Man-Kay Law, Taeik Kim, Kofi A. A. Makinwa:
Session 19 overview: Sensors and interfaces: Analog subcommittee. ISSCC 2018: 316-317 - 2017
- [j4]Hyunik Kim, Yongjo Kim, Taeik Kim, Hyung Jong Ko, SeongHwan Cho:
A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique. IEEE J. Solid State Circuits 52(11): 2934-2946 (2017) - [j3]Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 655-659 (2017) - 2016
- [c14]Hyunik Kim, Yongjo Kim, Taeik Kim, Hojin Park, SeongHwan Cho:
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS. ISSCC 2016: 328-329 - 2015
- [j2]Yudong Zhang, Woogeun Rhee, Taeik Kim, Hojin Park, Zhihua Wang:
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 736-740 (2015) - [c13]Joo-Myoung Kim, Jae-Seung Lee, Sun-a Kim, Taeik Kim, Hojin Park, Sang-Gug Lee:
A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS. CICC 2015: 1-4 - [c12]Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park:
15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology. ISSCC 2015: 1-3 - [c11]Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho:
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. ISSCC 2015: 1-3 - [c10]Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park:
14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology. ISSCC 2015: 1-3 - 2014
- [c9]Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park:
A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology. CICC 2014: 1-4 - [c8]Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park:
15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. ISSCC 2014: 268-269 - [c7]Sung-Jin Kim, Taeik Kim, Hojin Park:
A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology. VLSIC 2014: 1-2 - 2013
- [c6]Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. ISSCC 2013: 250-251 - [c5]Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park:
A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. ISSCC 2013: 254-255 - 2012
- [c4]Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park:
A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. ISSCC 2012: 240-242
2000 – 2009
- 2004
- [j1]Taeik Kim, Xiaoyong Li, David J. Allstot:
Compact model generation for on-chip transmission lines. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(3): 459-470 (2004) - [c3]Taeik Kim, David J. Allstot:
A tunable transmission line phase shifter (TTPS). ISCAS (1) 2004: 972-975 - 2003
- [c2]Srinivas Kodali, Taeik Kim, David J. Allstot:
On-chip inductor structures: a comparative study. ISCAS (1) 2003: 93-96 - [c1]Taeik Kim, Xiaoyong Li, David J. Allstot:
Accurate compact model extraction for on-chip coplanar waveguides. ISCAS (4) 2003: 644-647
Coauthor Index
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