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2020 – today
- 2024
[j96]Vaibhav Jain
, Devendra Kumar Sharma, Hari Mohan Gaur, Ashutosh Kumar Singh, Xiaoqing Wen:
Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation Computation. ACM Comput. Surv. 56(5): 120:1-120:36 (2024)- [j95]Qingping Zhang, Wenfa Zhan, Xiaoqing Wen:
A new die-level flexible design-for-test architecture for 3D stacked ICs. Integr. 97: 102190 (2024) - [j94]Aibin Yan, Han Bao, Wangjin Jiang, Jie Cui, Zhengfeng Huang, Xiaoqing Wen:
Efficient design approaches to CMOS full adder circuits. Microelectron. J. 149: 106235 (2024) - [j93]Zhengfeng Huang, Liting Sun, Xu Wang, Huaguo Liang, Yingchun Lu, Aibin Yan, Jun Pan, Xiaoqing Wen:
NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization. IEEE Trans. Aerosp. Electron. Syst. 60(4): 4590-4600 (2024) - [j92]Aibin Yan, Zhixing Li, Zhongyu Gao, Jing Zhang, Zhengfeng Huang, Tianming Ni, Jie Cui, Xiaolei Wang, Patrick Girard, Xiaoqing Wen:
MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2205-2214 (2024) - [j91]Aibin Yan, Yu Chen, Zhongyu Gao, Tianming Ni, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen:
FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2299-2303 (2024) - [j90]Tianming Ni, Xiaoqing Wen, Hussam Amrouch, Cheng Zhuo, Peilin Song:
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware. ACM Trans. Design Autom. Electr. Syst. 29(1): 1:1-1:3 (2024) - [j89]Aibin Yan, Litao Wang, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 116-127 (2024) - [c145]Aibin Yan, Chen Dong, Xing Guo, Jie Song, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen:
IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications. ACM Great Lakes Symposium on VLSI 2024: 19-24 - [c144]Aibin Yan, Zhuoyuan Lin, Guangzhu Liu, Qingyang Zhang, Zhengfeng Huang, Jie Cui, Xiaoqing Wen, Patrick Girard:
Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices. ISCAS 2024: 1-5 - [c143]Yang Chang, Guangzhu Liu, Inam Ullah, Gaoyang Shan, Xiaoqing Wen, Aibin Yan:
SHRCO: Design of an SRAM with High Reliability and Cost Optimization for Safety-Critical Applications. ITC-Asia 2024: 1-6 - [c142]Zhengfeng Huang, Yankun Lin, Fansheng Zeng, Jingchang Bian, Zhao Yang, Huaguo Liang, Yingchun Lu, Liang Yao, Xiaoqing Wen, Tianming Ni:
PFO PUF: A Lightweight Parallel Feed Obfuscation PUF Resistant to Machine Learning Attacks. ITC-Asia 2024: 1-6 - [c141]Xuehua Li, Jie Song, Chunjiong Zhang, Yuting He, Xiaoqing Wen, Zhengfeng Huang:
Multiple-Error Interceptive Voter Designs for Safety-Critical Applications. ITC-Asia 2024: 1-6 - [c140]Zhen Shen, Qingyang Zhang, Byeong-Hee Roh, Jie Song, Xiaoqing Wen:
CQCTL: A Cost-Optimized and Quadruple-Node-Upset Completely Tolerant Latch Design for Safety-Critical Applications. ITC-Asia 2024: 1-6 - [c139]Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen:
Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. ITC-Asia 2024: 1-6 - [c138]Fan Xia, Jing Zhang, Jehad Ali, Chunjiong Zhang, Xiaoqing Wen, Aibin Yan:
SRBML: A Single-Event-Upset Recoverable and BTI-Mitigated Latch Design for Long-Term Reliability Enhancement. ITC-Asia 2024: 1-5 - [c137]Jiajia Zhang, Zhenmin Li, Gaoyang Shan, Jie Song, Xing Guo, Xiaoqing Wen:
ICLTR: A Input-split Inverters and C-elements based Low-Cost Latch with Triple-Node-Upset Recovery. ITC-Asia 2024: 1-6 - [i5]Xiaoqing Wen, Quanbi Feng, Jianyu Niu, Yinqian Zhang, Chen Feng:
MECURY: Practical Cross-Chain Exchange via Trusted Hardware. CoRR abs/2409.14640 (2024) - [i4]Xiaoqing Wen, Quanbi Feng, Jianyu Niu, Yinqian Zhang, Chen Feng:
TeeRollup: Efficient Rollup Design Using Heterogeneous TEE. CoRR abs/2409.14647 (2024) - 2023
- [j88]Aibin Yan, Yuting He, Xiaoxiao Niu, Jie Cui, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications. IEEE Des. Test 40(4): 34-41 (2023) - [j87]Shiling Shi, Stefan Holst, Xiaoqing Wen:
GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting. IEICE Trans. Inf. Syst. 106(10): 1694-1704 (2023) - [j86]Zhenyu Guan, Zhiting Liu, Xiaoqing Wen, Qinjun Wan, Wenhan Xu:
Trusted fingerprint localization for multimedia devices based on blockchain. Inf. Sci. 643: 119231 (2023) - [j85]Aibin Yan, Jing Xiang, Yang Chang, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen:
Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications. Microelectron. J. 139: 105908 (2023) - [j84]Wenfa Zhan, Luping Zhang, Xuejun Feng, Pan Pan, Xueyuan Cai, Xiaoqing Wen:
An equivalent processing method for integrated circuit electrical parameter data using BP neural networks. Microelectron. J. 139: 105912 (2023) - [j83]Aibin Yan, Zhixing Li, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments. IEEE Trans. Aerosp. Electron. Syst. 59(3): 2885-2897 (2023) - [j82]Aibin Yan, Zhixing Li, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 2069-2073 (2023) - [j81]Tianming Ni, Qingsong Peng, Jingchang Bian, Liang Yao, Zhengfeng Huang, Aibin Yan, Senling Wang, Xiaoqing Wen:
Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5074-5085 (2023) - [j80]Aibin Yan, Runqi Liu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang:
Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2256-2260 (2023) - [j79]Aibin Yan, Aoran Cao, Zhengfeng Huang, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang:
Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications. IEEE Trans. Emerg. Top. Comput. 11(4): 1070-1081 (2023) - [j78]Deepika Saxena, Ishu Gupta, Rishabh Gupta, Ashutosh Kumar Singh, Xiaoqing Wen:
An AI-Driven VM Threat Prediction Model for Multi-Risks Analysis-Based Cloud Cybersecurity. IEEE Trans. Syst. Man Cybern. Syst. 53(11): 6815-6827 (2023) - [j77]Wu Zhou, Yiming Ouyang, Dongyu Xu, Zhengfeng Huang, Huaguo Liang, Xiaoqing Wen:
Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 442-455 (2023) - [j76]Dongyu Xu, Yiming Ouyang, Wu Zhou, Zhengfeng Huang, Huaguo Liang, Xiaoqing Wen:
RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2061-2074 (2023) - [c136]Tianming Ni, Fei Li, Qingsong Peng, Senling Wang, Xiaoqing Wen:
A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges. AsianHOST 2023: 1-6 - [c135]Mu Nie, Wen Jiang, Wankou Yang, Senling Wang, Xiaoqing Wen, Tianming Ni:
Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning. ATS 2023: 1-6 - [c134]Aibin Yan, Yu Chen, Zhengfeng Huang, Jie Cui, Xiaoqing Wen:
A High-Performance and P-Type FeFET-Based Non-Volatile Latch. ATS 2023: 1-5 - [c133]Aibin Yan, Xuehua Li, Zhongyu Gao, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen:
Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications. ATS 2023: 1-5 - [c132]Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. DATE 2023: 1-2 - [c131]Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni:
SASL-JTAG: A Light-Weight Dependable JTAG. DFT 2023: 1-3 - [c130]Aibin Yan, Xuehua Li, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen:
A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery. DSA 2023: 474-476 - [c129]Stefan Holst, Ruijun Ma, Xiaoqing Wen, Aibin Yan, Hui Xu:
BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell. ETS 2023: 1-6 - [c128]Aibin Yan, Shaojie Wei, Jinjun Zhang, Jie Cui, Jie Song, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications. ACM Great Lakes Symposium on VLSI 2023: 167-171 - [c127]Aibin Yan, Yang Chang, Jing Xiang, Hao Luo, Jie Cui, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen:
Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications. ACM Great Lakes Symposium on VLSI 2023: 293-298 - [c126]Aibin Yan, Shaojie Wei, Zhixing Li, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Design of Low-Cost Approximate CMOS Full Adders. ISCAS 2023: 1-5 - [c125]Aibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen:
Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications. ITC-Asia 2023: 1-6 - [c124]Aibin Yan, Fan Xia, Tianming Ni, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
A Low Overhead and Double-Node-Upset Self-Recoverable Latch. ITC-Asia 2023: 1-5 - [c123]Aibin Yan, Chao Zhou, Shaojie Wei, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness. ITC-Asia 2023: 1-6 - [c122]Shiling Shi, Stefan Holst, Xiaoqing Wen:
Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling. MCSoC 2023: 501-507 - [i3]Deepika Saxena, Ishu Gupta, Rishabh Gupta, Ashutosh Kumar Singh, Xiaoqing Wen:
An AI-Driven VM Threat Prediction Model for Multi-Risks Analysis-Based Cloud Cybersecurity. CoRR abs/2308.09578 (2023) - 2022
- [j75]Tianming Ni, Jingchang Bian, Zhao Yang, Mu Nie, Liang Yao, Zhengfeng Huang, Aibin Yan, Xiaoqing Wen:
Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement. IEEE Des. Test 39(5): 34-42 (2022) - [j74]Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu:
Evaluation and Test of Production Defects in Hardened Latches. IEICE Trans. Inf. Syst. 105-D(5): 996-1009 (2022) - [j73]Aibin Yan, Kuikui Qian, Tai Song, Zhengfeng Huang, Tianming Ni, Yu Chen, Xiaoqing Wen:
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications. Integr. 86: 22-29 (2022) - [j72]Deepika Saxena, Ishu Gupta, Jitendra Kumar, Ashutosh Kumar Singh, Xiaoqing Wen:
A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center. IEEE Syst. J. 16(2): 3163-3174 (2022) - [j71]Aibin Yan, Zhengzheng Fan, Liang Ding, Jie Cui, Zhengfeng Huang, Qijun Wang, Hao Zheng, Patrick Girard, Xiaoqing Wen:
Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications. IEEE Trans. Aerosp. Electron. Syst. 58(1): 517-529 (2022) - [j70]Qi Xu, Wenhao Sun, Song Chen, Yi Kang, Xiaoqing Wen:
Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1196-1208 (2022) - [j69]Qi Xu, Hao Geng, Tianming Ni, Song Chen, Bei Yu, Yi Kang, Xiaoqing Wen:
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3182-3187 (2022) - [j68]Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen:
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3492-3502 (2022) - [j67]Aibin Yan, Zhelong Xu, Xiangfeng Feng, Jie Cui, Zhili Chen, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments. IEEE Trans. Emerg. Top. Comput. 10(1): 404-413 (2022) - [c121]Tianming Ni, Qingsong Peng, Jingchang Bian, Liang Yao, Zhengfeng Huang, Aibin Yan, Xiaoqing Wen:
MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator. AsianHOST 2022: 1-6 - [c120]Aibin Yan, Liang Ding, Zhen Zhou, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen:
A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage. ATS 2022: 1-6 - [c119]Aibin Yan, Zhixing Li, Shiwei Huang, Zijie Zhai, Xiangyu Cheng, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard:
SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments. DATE 2022: 1257-1262 - [c118]Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui, Yong Zhou, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology. ACM Great Lakes Symposium on VLSI 2022: 255-260 - [c117]Aibin Yan, Zhihui He, Jing Xiang, Jie Cui, Yong Zhou, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications. ACM Great Lakes Symposium on VLSI 2022: 261-266 - [c116]Aibin Yan, Yu Chen, Shukai Song, Zijie Zhai, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications. ACM Great Lakes Symposium on VLSI 2022: 333-338 - [c115]Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara:
Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. ITC-Asia 2022: 43-48 - [c114]Aibin Yan, Shukai Song, Jixiang Zhang, Jie Cui, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard:
Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. ITC-Asia 2022: 73-78 - [c113]Kalyan Baital, Amlan Chakrabarti, Biswadeep Chatterjee, Stefan Holst, Xiaoqing Wen:
Power and Energy Safe Real-Time Multi-Core Task Scheduling. VLSID 2022: 16-21 - [c112]Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications. VTS 2022: 1-6 - 2021
- [j66]Aibin Yan, Aoran Cao, Zhelong Xu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications. J. Electron. Test. 37(4): 489-502 (2021) - [j65]Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian:
On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. IEICE Trans. Inf. Syst. 104-D(6): 816-827 (2021) - [j64]Aibin Yan, Zhihui He, Jun Zhou, Jie Cui, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications. Microelectron. J. 111: 105034 (2021) - [j63]Tianming Ni, Qi Xu, Zhengfeng Huang, Huaguo Liang, Aibin Yan, Xiaoqing Wen:
A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1952-1956 (2021) - [j62]Aibin Yan, Chaoping Lai, Yinlei Zhang, Jie Cui, Zhengfeng Huang, Jie Song, Jing Guo, Xiaoqing Wen:
Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS. IEEE Trans. Emerg. Top. Comput. 9(1): 520-533 (2021) - [j61]Tianming Ni, Zhao Yang, Hao Chang, Xiaoqiang Zhang, Lin Lu, Aibin Yan, Zhengfeng Huang, Xiaoqing Wen:
A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology. IEEE Trans. Emerg. Top. Comput. 9(2): 724-734 (2021) - [c111]Xiaoqing Wen:
LSI Testing: A Core Technology to a Successful LSI Industry. ASICON 2021: 1-4 - [c110]Stefan Holst, Lim Bumun, Xiaoqing Wen:
GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators. ATS 2021: 127-132 - [c109]Xiaoqing Wen, Zhenyu Guan, Dawei Li, Hanzheng Lyu, Huimin Li:
A Blockchain-based Framework for Information Management in Internet of Vehicles. CSCloud/EdgeCom 2021: 18-23 - [c108]Qi Xu, Junpeng Wang, Hao Geng, Song Chen, Xiaoqing Wen:
Reliability-Driven Neuromorphic Computing Systems Design. DATE 2021: 1586-1591 - [c107]Aibin Yan, Aoran Cao, Kuikui Qian, Liang Ding, Zhihui He, Zhengzheng Fan, Xiaoqing Wen:
A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets. DSA 2021: 734-736 - [c106]Aibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments. ACM Great Lakes Symposium on VLSI 2021: 301-306 - [c105]Aibin Yan, Liang Ding, Chuanbo Shan, Haoran Cai, Xiaofeng Chen, Zhanjun Wei, Zhengfeng Huang, Xiaoqing Wen:
TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation. ISCAS 2021: 1-5 - [c104]Zhenyu Guan, Xiaoqing Wen, Dawei Li, Mai Xu, Haihua Li:
A Blockchain-based Verified Locating Scheme for IoT Devices. ISPA/BDCloud/SocialCom/SustainCom 2021: 799-805 - [c103]Aibin Yan, Zijie Zhai, Lele Wang, Jixiang Zhang, Ningning Cui, Tianming Ni, Xiaoqing Wen:
Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing. ITC-Asia 2021: 1-5 - [c102]Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen:
A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch. NANOARCH 2021: 1-6 - [i2]Deepika Saxena, Ishu Gupta, Jitendra Kumar, Ashutosh Kumar Singh, Xiaoqing Wen:
A Secure and Multi-objective Virtual Machine Placement Framework for Cloud Data Centre. CoRR abs/2107.13502 (2021) - 2020
- [j60]Aibin Yan, Xiangfeng Feng, Yuanjie Hu, Chaoping Lai, Jie Cui, Zhili Chen, Kohei Miyase, Xiaoqing Wen:
Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments. IEEE Trans. Aerosp. Electron. Syst. 56(2): 1163-1171 (2020) - [j59]Aibin Yan, Zhelong Xu, Kang Yang, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. 56(4): 2666-2676 (2020) - [j58]Aibin Yan, Yan Chen, Zhelong Xu, Zhili Chen, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. 56(5): 3931-3940 (2020) - [j57]Aibin Yan, Yuanjie Hu, Jie Cui, Zhili Chen, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment. IEEE Trans. Computers 69(6): 789-799 (2020) - [j56]Tianming Ni, Yao Yao, Hao Chang, Lin Lu, Huaguo Liang, Aibin Yan, Zhengfeng Huang, Xiaoqing Wen:
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2938-2951 (2020) - [j55]Aibin Yan, Yafei Ling, Jie Cui, Zhili Chen, Zhengfeng Huang, Jie Song, Patrick Girard, Xiaoqing Wen:
Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 879-890 (2020) - [j54]Tianming Ni, Hao Chang, Tai Song, Qi Xu, Zhengfeng Huang, Huaguo Liang, Aibin Yan, Xiaoqing Wen:
Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC. IEEE Trans. Circuits Syst. 67-II(11): 2657-2661 (2020) - [j53]Aibin Yan, Yan Chen, Yuanjie Hu, Jun Zhou, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen:
Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets. IEEE Trans. Circuits Syst. 67-I(12): 4684-4695 (2020) - [j52]Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen:
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. 8(3): 591-601 (2020) - [c101]Aibin Yan, Yan Chen, Jun Zhou, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard:
A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets. ATS 2020: 1-5 - [c100]Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui, Zuobin Ying, Patrick Girard, Xiaoqing Wen:
HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications. DAC 2020: 1-6 - [c99]Aibin Yan, Zhelong Xu, Jie Cui, Zuobin Ying, Zhengfeng Huang, Huaguo Liang, Patrick Girard, Xiaoqing Wen:
Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications. ISCAS 2020: 1-5 - [c98]Stefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen:
Logic Fault Diagnosis of Hidden Delay Defects. ITC 2020: 1-10 - [c97]Zhengda Dou, Aibin Yan, Jun Zhou, Yuanjie Hu, Yan Chen, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen:
Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors. ITC-Asia 2020: 35-40
2010 – 2019
- 2019
- [j51]Aibin Yan, Jun Zhou, Yuanjie Hu, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen:
Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets. IEEE Access 7: 176188-176196 (2019) - [j50]Aibin Yan, Kang Yang, Zhengfeng Huang, Jiliang Zhang, Jie Cui, Xiangsheng Fang, Maoxiang Yi, Xiaoqing Wen:
A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 287-291 (2019) - [j49]Aibin Yan, Zhen Wu, Jing Guo, Jie Song, Xiaoqing Wen:
Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout. IEEE Trans. Reliab. 68(1): 354-363 (2019) - [j48]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c96]Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard, Xiaoqing Wen:
Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. ATS 2019: 43-48 - [c95]Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, Xiaoqing Wen, Patrick Girard:
Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications. ATS 2019: 55-60 - [c94]Aibin Yan, Yuanjie Hu, Jie Song, Xiaoqing Wen:
Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications. DATE 2019: 1679-1684 - [c93]Christian M. Fuchs, Pai H. Chou, Xiaoqing Wen, Nadia M. Murillo, Gianluca Furano, Stefan Holst, Antonis Tavoularis, Shyue-Kung Lu, Aske Plaat, Kostas Marinis:
A Fault-Tolerant MPSoC For CubeSats. DFT 2019: 1-6 - [c92]Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu:
STAHL: A Novel Scan-Test-Aware Hardened Latch Design. ETS 2019: 1-6 - [c91]Stefan Holst, Eric Schneider, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich:
Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. ITC 2019: 1-10 - [c90]Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara:
A Static Method for Analyzing Hotspot Distribution on the LSI. ITC-Asia 2019: 73-78 - [c89]Zhiyuan Song, Aibin Yan, Jie Cui, Zhili Chen, Xuejun Li, Xiaoqing Wen, Chaoping Lai, Zhengfeng Huang, Huaguo Liang:
A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells. ITC-Asia 2019: 139-144 - [c88]Stefan Holst, Shiling Shi, Xiaoqing Wen:
Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test. PRDC 2019: 124-129 - 2018
- [j47]Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen:
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1185-1196 (2018) - [c87]Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian:
Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. ATS 2018: 149-154 - [c86]Stefan Holst, Ruijun Ma, Xiaoqing Wen:
The impact of production defects on the soft-error tolerance of hardened latches. ETS 2018: 1-6 - 2017
- [j46]Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen:
Vernier ring based pre-bond through silicon vias test in 3D ICs. IEICE Electron. Express 14(18): 20170590 (2017) - [j45]Eric Schneider, Michael A. Kochte, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich:
GPU-Accelerated Simulation of Small Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 829-841 (2017) - [j44]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j43]Dong Xiang, Xiaoqing Wen, Laung-Terng Wang:
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 942-953 (2017) - [c85]Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian:
Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. ATS 2017: 145-150 - [c84]Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen:
Analysis and mitigation or IR-Drop induced scan shift-errors. ITC 2017: 1-8 - 2016
- [j42]Tian Chen, Dandan Shen, Xin Yi, Huaguo Liang, Xiaoqing Wen, Wei Wang:
Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures. IEICE Trans. Inf. Syst. 99-D(11): 2672-2681 (2016) - [j41]Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara:
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2310-2319 (2016) - [j40]Dong Xiang, Kele Shen, Bhargab B. Bhattacharya, Xiaoqing Wen, Xijiang Lin:
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 499-512 (2016) - [j39]Wei-Sheng Ding, Hung-Yi Hsieh, Cheng-Yu Han, James Chien-Mo Li, Xiaoqing Wen:
Test Pattern Modification for Average IR-Drop Reduction. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 38-49 (2016) - [c83]Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte:
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. ATS 2016: 19-24 - [c82]Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen:
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. ATS 2016: 173-178 - [c81]Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian:
On Optimal Power-Aware Path Sensitization. ATS 2016: 179-184 - [c80]Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen:
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS 2016: 203-208 - [c79]Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen:
SAT-based post-processing for regional capture power reduction in at-speed scan test generation. ETS 2016: 1-6 - [c78]Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen:
Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM. ISVLSI 2016: 679-684 - 2015
- [c77]Xiaoqing Wen:
Power supply noise and its reduction in at-speed scan testing. ASICON 2015: 1-4 - [c76]Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian:
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. ATS 2015: 103-108 - [c75]Eric Schneider, Stefan Holst, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich:
GPU-accelerated small delay fault simulation. DATE 2015: 1174-1179 - [c74]Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara:
Identification of high power consuming areas with gate type and logic level information. ETS 2015: 1-6 - [c73]Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase:
A soft-error tolerant TCAM using partial don't-care keys. ETS 2015: 1-2 - 2014
- [j38]Hongwei Yin, Xiaoyong Xiao, Xiaoqing Wen, Kai Liu:
Pattern analysis of a modified Leslie-Gower predator-prey model with Crowley-Martin functional response and diffusion. Comput. Math. Appl. 67(8): 1607-1621 (2014) - [j37]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. 97-D(10): 2706-2718 (2014) - [c72]Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase:
Soft-error tolerant TCAMs for high-reliability packet classifications. APCCAS 2014: 471-474 - [c71]Eric Schneider, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich:
Data-parallel simulation for fast and accurate timing validation of CMOS circuits. ICCAD 2014: 17-23 - 2013
- [j36]Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte:
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. IEEE Des. Test 30(4): 60-70 (2013) - [j35]Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara:
A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing. IEICE Trans. Inf. Syst. 96-D(9): 2003-2011 (2013) - [j34]Hongwei Yin, Xiaoyong Xiao, Xiaoqing Wen, Tianshou Zhou:
Stability of regulatory protein Gradients induced by morphogen DPP in Drosophila wing Disc. Int. J. Bifurc. Chaos 23(8) (2013) - [c70]Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium 2013: 19-24 - [c69]Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara:
Search Space Reduction for Low-Power Test Generation. Asian Test Symposium 2013: 171-176 - [c68]Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang:
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design 2013: 279-284 - 2012
- [j33]Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen:
Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. J. Low Power Electron. 8(2): 248-258 (2012) - [j32]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang:
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17(4): 48:1-48:16 (2012) - [c67]Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen:
A Transition Isolation Scan Cell Design for Low Shift and Capture Power. Asian Test Symposium 2012: 107-112 - [c66]Xiaoqing Wen, Sudhakar M. Reddy:
Session Summary III: Power-Aware Testing: Present and Future. Asian Test Symposium 2012: 220 - [c65]Xiaoqing Wen:
Power-aware testing: The next stage. ETS 2012: 1 - [c64]Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On pinpoint capture power management in at-speed scan test generation. ITC 2012: 1-10 - [c63]Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara:
A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. VTS 2012: 197-202 - 2011
- [j31]Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara:
A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing. IEICE Trans. Inf. Syst. 94-D(4): 833-840 (2011) - [j30]Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. 94-D(6): 1216-1226 (2011) - [j29]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu:
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 455-463 (2011) - [c62]Xiaoqing Wen:
Towards the next generation of low-power test technologies. ASICON 2011: 232-235 - [c61]Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 - [c60]Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich:
Efficient BDD-based Fault Simulation in Presence of Unknown Values. Asian Test Symposium 2011: 383-388 - [c59]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen:
Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium 2011: 506-510 - [c58]Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara:
Transition-Time-Relation based capture-safety checking for at-speed scan test generation. DATE 2011: 895-898 - [c57]Xiaoqing Wen:
VLSI testing and test power. IGCC 2011: 1-6 - [c56]Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich:
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED 2011: 33-38 - [c55]Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen:
Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. ITC 2011: 1-7 - [c54]Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang:
A novel scan segmentation design method for avoiding shift timing failure in scan testing. ITC 2011: 1-8 - [c53]Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg:
Special session 5B: Panel How much toggle activity should we be testing with? VTS 2011: 114 - [c52]Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor:
Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS 2011: 166-171 - 2010
- [j28]Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. 93-D(1): 2-9 (2010) - [j27]Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1309-1318 (2010) - [j26]Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen:
On Delay Test Quality for Test Cubes. Inf. Media Technol. 5(4): 1147-1155 (2010) - [j25]Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen:
On Delay Test Quality for Test Cubes. IPSJ Trans. Syst. LSI Des. Methodol. 3: 283-291 (2010) - [j24]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed:
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. 6(2): 359-374 (2010) - [j23]Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone:
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 299-312 (2010) - [c51]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen:
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381 - [c50]Nor Azura Zakaria, Edward V. Bautista Jr., Suhaimi Bahisham Jusoh, Weng Fook Lee, Xiaoqing Wen:
Case Studies on Transition Fault Test Generation for At-speed Scan Testing. DFT 2010: 180-188 - [c49]Xiaoqing Wen:
Low-Power Testing for Low-Power Devices. DFT 2010: 261 - [c48]Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen:
Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs. DFT 2010: 331-339 - [c47]Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang:
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. DFT 2010: 358-366 - [c46]Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura:
On estimation of NBTI-Induced delay degradation. ETS 2010: 107-111 - [c45]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed:
Is test power reduction through X-filling good enough? ITC 2010: 805
2000 – 2009
- 2009
- [j22]Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Des. Test Comput. 26(1): 26-35 (2009) - [j21]Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase:
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1767-1776 (2009) - [c44]Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa:
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium 2009: 99-104 - [c43]Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara:
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD 2009: 97-104 - [c42]Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara:
A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. PRDC 2009: 81-86 - 2008
- [j20]Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu:
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Des. Test Comput. 25(2): 122-130 (2008) - [j19]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. 24(4): 379-391 (2008) - [j18]Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara:
A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits. IEICE Trans. Inf. Syst. 91-D(3): 667-674 (2008) - [j17]Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy:
On Detection of Bridge Defects with Stuck-at Tests. IEICE Trans. Inf. Syst. 91-D(3): 683-689 (2008) - [j16]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of Delay Test Quality and Its Application to Test Generation. Inf. Media Technol. 3(4): 717-728 (2008) - [j15]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of Delay Test Quality and Its Application to Test Generation. IPSJ Trans. Syst. LSI Des. Methodol. 1: 104-115 (2008) - [j14]C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen:
Test Strategies for Low-Power Devices. J. Low Power Electron. 4(2): 127-138 (2008) - [c41]Shianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami:
Practical Challenges in Logic BIST Implementation. ATS 2008: 265 - [c40]Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS 2008: 397-402 - [c39]Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen:
Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008 - [c38]C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen:
Test Strategies for Low Power Devices. DATE 2008: 728-733 - [c37]Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen:
Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS 2008: 263-266 - [c36]Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte:
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT 2008: 143-151 - [c35]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS 2008: 55-60 - [c34]Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58 - [c33]Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li:
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. ITC 2008: 1-9 - [c32]Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase:
Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing. ITC 2008: 1-10 - 2007
- [j13]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. 90-D(9): 1398-1405 (2007) - [c31]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja:
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC 2007: 527-532 - [c30]Nicola Nicolici, Xiaoqing Wen:
Embedded Tutorial on Low Power Test. ETS 2007: 202-210 - [c29]Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of delay test quality and its application to test generation. ICCAD 2007: 413-417 - [c28]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang:
A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC 2007: 1-10 - [i1]B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu:
At-Speed Logic BIST for IP Cores. CoRR abs/0710.4645 (2007) - 2006
- [j12]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. 89-D(5): 1679-1686 (2006) - [j11]Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen:
Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Trans. Inf. Syst. 89-D(10): 2616-2625 (2006) - [j10]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Per-Test Fault Diagnosis Method Based on the X-Fault Model. IEICE Trans. Inf. Syst. 89-D(11): 2756-2765 (2006) - [c27]Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC 2006: 348-353 - [c26]Yu Hu, Cheng Li, Jia Li, Yinhe Han, Xiaowei Li, Wei Wang, Hua-Wei Li, Laung-Terng Wang, Xiaoqing Wen:
Test data compression based on clustered random access scan. ATS 2006: 231-236 - [c25]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD 2006: 251-258 - [c24]Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu:
A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. ITC 2006: 1-10 - [c23]Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
A Framework of High-quality Transition Fault ATPG for Scan Circuits. ITC 2006: 1-6 - [c22]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita:
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS 2006: 58-65 - 2005
- [j9]Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. IEICE Trans. Inf. Syst. 88-D(4): 703-710 (2005) - [j8]Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen:
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Trans. Inf. Syst. 88-D(9): 2126-2134 (2005) - [j7]Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
Fault Diagnosis of Physical Defects Using Unknown Behavior Model. J. Comput. Sci. Technol. 20(2): 187-194 (2005) - [j6]Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja:
Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electron. 1(3): 319-330 (2005) - [c21]Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty:
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. ASP-DAC 2005: 59-64 - [c20]Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy:
On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium 2005: 216-223 - [c19]Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
Path delay test compaction with process variation tolerance. DAC 2005: 845-850 - [c18]B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu:
At-Speed Logic BIST for IP Cores. DATE 2005: 860-861 - [c17]Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo:
At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478 - [c16]Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang:
UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. ITC 2005: 8 - [c15]Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low-capture-power test generation for scan-based at-speed testing. ITC 2005: 10 - [c14]Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen:
Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC 2005: 175-182 - [c13]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On Low-Capture-Power Test Generation for Scan Testing. VTS 2005: 265-270 - 2004
- [c12]Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On per-test fault diagnosis using the X-fault model. ICCAD 2004: 633-640 - [c11]Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai:
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. ITC 2004: 916-925 - 2003
- [c10]Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
Fault Diagnosis for Physical Defects of Unknown Behaviors. Asian Test Symposium 2003: 236-241 - 2001
- [c9]Xiaoqing Wen, Hsin-Po Wang:
A Flexible Logic BIST Scheme and Its Application to SoC Designs. Asian Test Symposium 2001: 463
1990 – 1999
- 1999
- [j5]Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto:
Random pattern testable design with partial circuit duplication and IDDQ testing. Syst. Comput. Jpn. 30(5): 18-27 (1999) - 1998
- [c8]Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
Design for Diagnosability of CMOS Circuits. Asian Test Symposium 1998: 144-149 - 1997
- [j4]Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita:
IDDQ test vector selection for transistor short fault testing. Syst. Comput. Jpn. 28(5): 11-21 (1997) - [c7]Xiaoqing Wen:
Fault Diagnosis for Static CMOS Circuits. Asian Test Symposium 1997: 282-287 - [c6]Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto:
Random Pattern Testable Design with Partial Circuit Duplication. Asian Test Symposium 1997: 353-358 - 1996
- [c5]Xiaoqing Wen, Kewal K. Saluja:
A new method towards achieving global optimality in technology mapping. ICCAD 1996: 9-12 - 1995
- [j3]Xiaoqing Wen, Kozo Kinoshita, Hideo Tamamoto, Hiroshi Yokoyama:
Efficient Guided-Probe Fault Location Method for Sequential Circuits. IEICE Trans. Inf. Syst. 78-D(2): 122-129 (1995) - [j2]Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita:
Testing of k-FR Circuits under Highly Observable Condition. IEICE Trans. Inf. Syst. 78-D(7): 830-838 (1995) - [c4]Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita:
Transistor leakage fault location with ZDDQ measurement. Asian Test Symposium 1995: 51-57 - 1992
- [j1]Xiaoqing Wen, Kozo Kinoshita:
A Testable Design of Logic Circuits under Highly Observable Condition. IEEE Trans. Computers 41(5): 654-659 (1992) - [c3]Xiaoqing Wen, Kozo Kinoshita:
Testable Designs of Sequential Circuits Under Highly Observable Condition. ITC 1992: 632-641 - 1990
- [c2]Xiaoqing Wen, Kozo Kinoshita:
Fault detection and diagnosis of k-UCP circuits under totally observable condition. FTCS 1990: 382-389 - [c1]Xiaoqing Wen, Kozo Kinoshita:
A testable design of logic circuits under highly observable condition. ITC 1990: 955-963
Coauthor Index
[j92] [j91] [j89] [c145] [c144] [j88] [j85] [j83] [j82] [j80] [j79] [c132] [c128] [c126] [c125] [c124] [c123] [j71] [j67] [c120] [c119] [c118] [c117] [c116] [c114] [c112] [j66] [j64] [c106] [j59] [j58] [j57] [j55] [j53] [c101] [c100] [c99] [c97] [j51] [c96] [c95] [j37] [c70] [j33] [c64] [c61] [c59] [c52] [j28] [j24] [c51] [c45] [c40] [c39] [c28]
[j94] [j93] [j92] [j91] [j89] [c144] [c142] [c141] [j88] [j85] [j83] [j82] [j81] [j79] [j77] [j76] [c134] [c133] [c132] [c130] [c127] [c126] [c125] [c124] [c123] [j75] [j73] [j71] [j67] [c121] [c120] [c117] [c116] [c114] [c112] [j64] [j63] [j62] [j61] [c105] [c102] [j59] [j58] [j57] [j56] [j55] [j54] [c99] [j51] [j50] [c89] [j46]
[c115] [j65] [j52] [c90] [c87] [c85] [c84] [j41] [c83] [c80] [c76] [c74] [j37] [j36] [j35] [c70] [c69] [c68] [c64] [c63] [j31] [j30] [c61] [c58] [c56] [c54] [c52] [j28] [j27] [j26] [j25] [c46] [c44] [c43] [c42] [j19] [j18] [j17] [j16] [j15] [c40] [c37] [c35] [c34] [j13] [c31] [c29] [c28] [j12] [j10] [c27] [c25] [c23] [c22] [j9] [j6] [c21] [c20] [c19] [c15] [c13] [c12]
[c115] [j65] [j60] [c90] [c87] [c85] [c84] [j41] [c82] [c81] [c79] [c76] [c74] [c73] [j37] [c72] [j36] [j35] [c69] [c68] [c64] [c63] [j31] [j30] [c61] [c60] [c59] [c58] [c56] [c54] [c52] [j28] [j27] [j26] [j25] [c46] [c45] [j21] [c44] [c43] [c42] [j19] [j18] [j17] [c40] [c37] [c35] [c34] [c32] [j13] [c31] [c28] [j10] [c25] [c22] [j6] [c20]
Mark M. Tehranipoor
aka: Mohammad Tehranipoor
aka: Mohammad Tehranipoor
[j94] [j93] [j92] [j91] [j89] [c145] [c144] [c143] [c138] [j88] [j85] [j83] [j82] [j81] [j80] [j79] [c134] [c133] [c132] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [j75] [j74] [j73] [j71] [j67] [c121] [c120] [c119] [c118] [c117] [c116] [c114] [c112] [j66] [j64] [j63] [j62] [j61] [c107] [c106] [c105] [c103] [c102] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [j53] [c101] [c100] [c99] [c97] [j51] [j50] [j49] [c96] [c95] [c94] [c92] [c89]
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