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2010 – 2019
- 2019
[c16]Algirdas V. Avizienis, Rimas Avizienis, Audrius V. Avizienis:
The STAR-Guardian Network for the Protection of Long-Life Cyber-Physical Systems. DSN (Supplements) 2019: 7-8- 2017
- [c15]Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael S. Georgas, Andrew S. Waterman, Jeffrey M. Shainline, Rimas R. Avizienis, Sen Lin, Benjamin R. Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry M. Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic:
Microprocessor chip with photonic I/O. OFC 2017: 1-3 - 2016
- [j4]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4): 930-942 (2016) - [j3]Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic:
An Agile Approach to Building RISC-V Microprocessors. IEEE Micro 36(2): 8-20 (2016) - [c14]Algirdas Avizienis, Rimas Avizienis, Audrius V. Avizienis:
The Concept of a Software-Free Resilience Infrastructure for Cyber-Physical Systems. DSN Workshops 2016: 230-233 - 2015
- [j2]Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael Georgas, Andrew Waterman, Jeffrey M. Shainline, Rimas Avizienis, Sen Lin, Benjamin Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic:
Single-chip microprocessor that communicates directly using light. Nat. 528(7581): 534-538 (2015) - [c13]Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic:
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium 2015: 1-45 - [c12]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC 2015: 316- - 2014
- [c11]Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovic, Krste Asanovic:
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. ESSCIRC 2014: 199-202 - 2013
- [j1]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators. ACM Trans. Comput. Syst. 31(3): 6 (2013) - [c10]Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David A. Patterson, Krste Asanovic:
The RISC-V instruction set. Hot Chips Symposium 2013: 1 - 2012
- [c9]Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic:
Chisel: constructing hardware in a Scala embedded language. DAC 2012: 1216-1225 - 2011
- [c8]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
The Maven vector-thread architecture. Hot Chips Symposium 2011: 1 - [c7]Juan A. Colmenares, Ian Saxton, Eric Battenberg, Rimas Avizienis, Nils Peters, Krste Asanovic, John Kubiatowicz, David Wessel:
Real-time Musical Applications on an Experimental Operating System for Multi-Core Processors. ICMC 2011 - [c6]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators. ISCA 2011: 129-140 - 2010
- [c5]Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic:
RAMP gold: an FPGA-based architecture simulator for multiprocessors. DAC 2010: 463-468
2000 – 2009
- 2007
- [c4]David Wessel, Rimas Avizienis, Adrian Freed, Matthew Wright:
A Force Sensitive Multi-Touch Array Supporting Multiple 2-D Musical Control Structures. NIME 2007: 41-45 - 2006
- [c3]Adrian Freed, Rimas Avizienis, Matthew Wright:
Beyond 0-5V: Expanding Sensor Integration Architectures. NIME 2006: 97-100 - 2000
- [c2]Rimas Avizienis, Adrian Freed, Takahiko Suzuki, David Wessel:
Scalable Connectivity Processor for Computer Music Performance Systems. ICMC 2000 - [c1]Adrian Freed, Rimas Avizienis:
A New Music Keyboard with Continuous Key-position Sensing and High-speed Communication. ICMC 2000
Coauthor Index
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