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Ruth Iris Bahar – Iris Bahar
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2020 – today
- 2024
[j39]Samuel Thomas
, Kidus Workneh, Ange-Thierry Ishimwe, Zack McKevitt, Phaedra S. Curlin, R. Iris Bahar, Joseph Izraelevitz, Tamara Lehman:
Baobab Merkle Tree for Efficient Secure Memory. IEEE Comput. Archit. Lett. 23(1): 33-36 (2024)- [c97]Samuel Thomas, Kidus Workneh, Jac McCarty, Joseph Izraelevitz, Tamara Lehman, R. Iris Bahar:
A Midsummer Night's Tree: Efficient and High Performance Secure SCM. ASPLOS (3) 2024: 22-37 - 2023
- [c96]Semanti Basu, Peter Bajcsy, Thomas E. Cleveland IV, Manuel J. Carrasco, R. Iris Bahar:
LipoPose: Adapting Cellpose to Lipid Nanoparticle Segmentation. BIOIMAGING 2023: 115-123 - 2022
- [c95]Yanqi Liu, Anthony Opipari, Théo Guérin, Ruth Iris Bahar:
Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation. FPGA 2022: 51 - [c94]Samuel Thomas, Jiwon Choe, Ofir Gordon, Erez Petrank, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Towards Hardware Accelerated Garbage Collection with Near-Memory Processing. HPEC 2022: 1-6 - [c93]Yanqi Liu, Anthony Opipari, Odest Chadwicke Jenkins, R. Iris Bahar:
A Reconfigurable Hardware Library for Robot Scene Perception. ICCAD 2022: 101:1-101:9 - [c92]R. Iris Bahar:
EDAML 2022 Invited Speaker 3: Scalable ML Architectures for Real-time Energy-efficient Computing. IPDPS Workshops 2022: 1184 - [c91]Casey Nelson, Joseph Izraelevitz, R. Iris Bahar, Tamara Silbergleit Lehman:
Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing. SEED 2022: 179-189 - [c90]Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. SPAA 2022: 321-332 - 2021
- [c89]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar:
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. ITC 2021: 319-323 - [i7]Semir Tatlidil, Yanqi Liu, Emily Sheetz, R. Iris Bahar, Steven A. Sloman:
Using Human-Guided Causal Knowledge for More Generalized Robot Task Planning. CoRR abs/2110.04664 (2021) - 2020
- [j38]Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu:
Voltage Noise Mitigation With Barrier Approximation. IEEE Comput. Archit. Lett. 19(2): 155-158 (2020) - [c88]Yanqi Liu, Giuseppe Calderoni, Ruth Iris Bahar:
Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. FPL 2020: 284-290 - [c87]Yanqi Liu, Can Eren Derman, Giuseppe Calderoni, R. Iris Bahar:
Hardware Acceleration of Robot Scene Perception Algorithms. ICCAD 2020: 164:1-164:8 - [i6]R. Iris Bahar, Alex K. Jones, Srinivas Katkoori, Patrick H. Madden, Diana Marculescu, Igor L. Markov:
Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond. CoRR abs/2005.01588 (2020) - [i5]Yanqi Liu, Giuseppe Calderoni, R. Iris Bahar:
Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. CoRR abs/2007.07425 (2020)
2010 – 2019
- 2019
- [j37]R. Iris Bahar:
Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018). IEEE Des. Test 36(2): 98-99 (2019) - [j36]Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J. Electron. Test. 35(6): 887-900 (2019) - [j35]Kumud Nepal, Soheil Hashemi, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Automated High-Level Generation of Low-Power Approximate Computing Circuits. IEEE Trans. Emerg. Top. Comput. 7(1): 18-30 (2019) - [c86]Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar:
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. DATE 2019: 1571-1574 - [c85]Iris Bahar:
Energy-efficient and Sustainable Computing across the Hardware/Software Stack. IGSC 2019: 1 - [c84]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Test Architecture for Fine Grained Capture Power Reduction. ICECS 2019: 558-561 - [c83]Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu:
Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis. IISWC 2019: 263-267 - [c82]Xiaotong Chen, Rui Chen, Zhiqiang Sui, Zhefan Ye, Yanqi Liu, R. Iris Bahar, Odest Chadwicke Jenkins:
GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments. IROS 2019: 3988-3995 - [c81]Jiwon Choe, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Attacking memory-hard scrypt with near-data-processing. MEMSYS 2019: 33-37 - [c80]Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. SPAA 2019: 297-308 - [c79]R. Iris Bahar, Ulya R. Karpuzcu, Sasa Misailovic:
Special Session: Does Approximation Make Testing Harder (or Easier)? VTS 2019: 1-9 - [e5]Iris Bahar, Maurice Herlihy, Emmett Witchel, Alvin R. Lebeck:
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019, Providence, RI, USA, April 13-17, 2019. ACM 2019, ISBN 978-1-4503-6240-5 [contents] - [i4]Xiaotong Chen, Rui Chen, Zhiqiang Sui, Zhefan Ye, Yanqi Liu, R. Iris Bahar, Odest Chadwicke Jenkins:
GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments. CoRR abs/1903.08352 (2019) - 2018
- [j34]Sri Parameswaran, R. Iris Bahar, David Z. Pan:
Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). IEEE Des. Test 35(2): 101-102 (2018) - [j33]Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. Int. J. Parallel Program. 46(6): 1304-1328 (2018) - [j32]Christopher B. Harris, R. Iris Bahar:
Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems. J. Low Power Electron. 14(1): 148-156 (2018) - [j31]Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 643-656 (2018) - [c78]Yanqi Liu, Alessandro Costantini, R. Iris Bahar, Zhiqiang Sui, Zhefan Ye, Shiyang Lu, Odest Chadwicke Jenkins:
Robust object estimation using generative-discriminative inference for secure robotics applications. ICCAD 2018: 75 - [e4]Iris Bahar:
Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018. ACM 2018, ISBN 978-1-4503-5950-4 [contents] - 2017
- [j30]Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. ACM Trans. Embed. Comput. Syst. 16(5s): 153:1-153:18 (2017) - [c77]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. DAC 2017: 28:1-28:6 - [c76]Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Understanding the impact of precision quantization on the accuracy and energy of neural networks. DATE 2017: 1474-1479 - [c75]Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar:
Evaluating critical bits in arithmetic operations due to timing violations. HPEC 2017: 1-7 - [c74]Christopher B. Picardo, Justin G. R. Delva, R. Iris Bahar:
Comprehensive comparison of gradient-based cross-spectral stereo matching generated disparity maps. MWSCAS 2017: 200-204 - [c73]Christopher B. Harris, R. Iris Bahar:
A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots. NGCAS 2017: 25-28 - [i3]Hokchhay Tann, Soheil Hashemi, Iris Bahar, Sherief Reda:
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. CoRR abs/1705.04288 (2017) - 2016
- [c72]Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar:
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. CASES 2016: 20:1-20:10 - [c71]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Runtime configurable deep neural networks for energy-accuracy trade-off. CODES+ISSS 2016: 34:1-34:10 - [c70]Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A fast simulator for the analysis of sub-threshold thermal noise transients. DAC 2016: 56:1-56:6 - [c69]Soheil Hashemi, R. Iris Bahar, Sherief Reda:
A low-power dynamic divider for approximate applications. DAC 2016: 105:1-105:6 - [c68]Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar:
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. FPL 2016: 1-9 - [c67]Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson:
Design of Error-Resilient Logic Gates with Reinforcement Using Implications. ACM Great Lakes Symposium on VLSI 2016: 191-196 - [c66]Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter:
Using Existing Reconfigurable Logic in 3D Die Stacks for Test. NATW 2016: 46-52 - [i2]Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off. CoRR abs/1607.05418 (2016) - [i1]Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda:
Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks. CoRR abs/1612.03940 (2016) - 2015
- [j29]Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan:
Repairing a 3-D Die-Stack Using Available Programmable Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 849-861 (2015) - [j28]Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems. ACM Trans. Embed. Comput. Syst. 14(3): 51:1-51:27 (2015) - [j27]R. Iris Bahar, Alex K. Jones, Yuan Xie:
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems. ACM Trans. Design Autom. Electr. Syst. 20(4): 59:1-59:2 (2015) - [c65]Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. ACM Great Lakes Symposium on VLSI 2015: 9-14 - [c64]Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits. ACM Great Lakes Symposium on VLSI 2015: 45-50 - [c63]Soheil Hashemi, R. Iris Bahar, Sherief Reda:
DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. ICCAD 2015: 418-425 - [c62]Jun Wang, Iris Bahar:
Message from the program co-chairs. NAS 2015: 1 - 2014
- [j26]Onur Ulusel, Kumud Nepal, R. Iris Bahar, Sherief Reda:
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. ACM Trans. Reconfigurable Technol. Syst. 7(1): 4:1-4:22 (2014) - [c61]Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda:
ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. DATE 2014: 1-6 - [c60]Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Speculative synchronization for coherence-free embedded NUMA architectures. ICSAMOS 2014: 99-106 - 2013
- [c59]Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Built-in Self-Repair in a 3D die stack using programmable logic. DFTS 2013: 243-248 - [c58]Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini:
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. MES 2013: 58-61 - [c57]Dimitra Papagiannopoulou, Patipan Prasertsom, R. Iris Bahar:
Flexible data allocation for scratch-pad memories to reduce NBTI effects. ISQED 2013: 60-67 - [c56]R. Iris Bahar, Alex K. Jones, Srinivas Katkoori, Patrick H. Madden, Diana Marculescu, Igor L. Markov:
"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation. MSE 2013: 64-67 - 2012
- [j25]Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera:
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. J. Electron. Test. 28(3): 349-363 (2012) - [j24]Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar:
Using implications to choose tests through suspect fault identification. ACM Trans. Design Autom. Electr. Syst. 18(1): 14:1-14:19 (2012) - [c55]Roto Le, Joseph L. Mundy, R. Iris Bahar:
High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System. ASAP 2012: 16-23 - [c54]Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda:
Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. FCCM 2012: 65-68 - [c53]Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy:
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. ACM Great Lakes Symposium on VLSI 2012: 39-44 - 2011
- [j23]Desta Tadesse, R. Iris Bahar, Joel Grodstein:
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. J. Electron. Test. 27(2): 123-136 (2011) - [c52]Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy:
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. CODES+ISSS 2011: 39-48 - [c51]Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar:
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. ETS 2011: 211 - [c50]Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera:
NBTI-aware data allocation strategies for scratchpad memory based embedded systems. LATW 2011: 1-6 - [c49]Roto Le, R. Iris Bahar, Joseph L. Mundy:
A novel parallel Tier-1 coder for JPEG2000 using GPUs. SASP 2011: 129-136 - [c48]Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Enhancing online error detection through area-efficient multi-site implications. VTS 2011: 241-246 - 2010
- [j22]Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. J. Parallel Distributed Comput. 70(10): 1042-1052 (2010) - [j21]Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino:
Dual-Vt assignment policies in ITD-aware synthesis. Microelectron. J. 41(9): 547-553 (2010) - [j20]Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 788-801 (2010) - [j19]Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino:
Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1608-1620 (2010) - [c47]Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI 2010: 131-134 - [c46]Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. ACM Great Lakes Symposium on VLSI 2010: 281-286 - [c45]Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. HiPEAC 2010: 50-65 - [e3]R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand:
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010. ACM 2010, ISBN 978-1-4503-0012-4 [contents] - [e2]Shamik Das, Iris Bahar, Michael T. Niemier:
2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-8020-3 [contents]
2000 – 2009
- 2009
- [j18]R. Iris Bahar:
Introduction to special section: Best of NANOARCH 2008. ACM J. Emerg. Technol. Comput. Syst. 5(2): 6:1 (2009) - [c44]Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
Detecting errors using multi-cycle invariance information. DATE 2009: 791-796 - [c43]Roto Le, Sherief Reda, R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA 2009: 286 - [c42]Cesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino:
Energy-optimal synchronization primitives for single-chip multi-processors. ACM Great Lakes Symposium on VLSI 2009: 141-144 - [c41]Roto Le, Sherief Reda, R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI 2009: 251-256 - [c40]Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Compacting test vector sets via strategic use of implications. ICCAD 2009: 83-88 - [c39]Sherief Reda, Aung Si, R. Iris Bahar:
Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ISLPED 2009: 283-286 - [c38]Desta Tadesse, Joel Grodstein, R. Iris Bahar:
AutoRex: An automated post-silicon clock tuning tool. ITC 2009: 1-10 - [e1]Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar:
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009. ACM 2009, ISBN 978-1-60558-522-2 [contents] - 2008
- [j17]R. Iris Bahar, Krishnendu Chakrabarty:
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. ACM J. Emerg. Technol. Comput. Syst. 4(2): 5:1-5:2 (2008) - [j16]Cesare Ferri, Sherief Reda, R. Iris Bahar:
Parametric yield management for 3D ICs: Models and strategies for improvement. ACM J. Emerg. Technol. Comput. Syst. 4(4): 19:1-19:22 (2008) - [j15]Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino:
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electron. 4(3): 374-384 (2008) - [j14]R. Iris Bahar, Krishnendu Chakrabarty:
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. ACM Trans. Design Autom. Electr. Syst. 13(2): 36:1-36:2 (2008) - [c37]Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar:
Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI 2008: 5-10 - [c36]Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy efficient synchronization techniques for embedded architectures. ACM Great Lakes Symposium on VLSI 2008: 435-440 - [c35]Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino:
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED 2008: 217-220 - [c34]Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar:
Using Implications for Online Error Detection. ITC 2008: 1-10 - [c33]Desta Tadesse, R. Iris Bahar, Joel Grodstein:
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. VTS 2008: 339-344 - 2007
- [j13]R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram:
Architectures for Silicon Nanoelectronics and Beyond. Computer 40(1): 25-33 (2007) - [j12]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electron. Test. 23(2-3): 255-266 (2007) - [j11]Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy:
A hardware/software framework for supporting transactional memory in a MPSoC environment. SIGARCH Comput. Archit. News 35(1): 47-54 (2007) - [c32]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE 2007: 576-581 - [c31]Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein:
Accurate timing analysis using SAT and pattern-dependent delay models. DATE 2007: 1018-1023 - [c30]Cesare Ferri, Sherief Reda, R. Iris Bahar:
Strategies for improving the parametric yield and profits of 3D ICs. ICCAD 2007: 220-226 - [c29]Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar:
Thermally-induced soft errors in nanoscale CMOS circuits. NANOARCH 2007: 62-69 - 2006
- [j10]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26(5): 19-27 (2006) - [j9]Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein:
Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1815-1830 (2006) - [c28]Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss:
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. DAC 2006: 705-708 - [c27]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing MRF based error correcting circuits for memory elements. DATE 2006: 792-793 - [c26]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI 2006: 149-152 - [c25]R. Iris Bahar:
Trends and Future Directions in Nano Structure Based Computing and Fabrication. ICCD 2006: 522-527 - [c24]Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy implications of multiprocessor synchronization. SPAA 2006: 329 - 2005
- [j8]R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi:
Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. IEEE Des. Test Comput. 22(4): 295-297 (2005) - [j7]R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein:
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 502-515 (2005) - [c23]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing logic circuits for probabilistic computation in the presence of noise. DAC 2005: 485-490 - [c22]Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy reduction in multiprocessor systems using transactional memory. ISLPED 2005: 331-334 - 2004
- [j6]Yu Bai, R. Iris Bahar:
A low-power in-order/out-of-order issue queue. ACM Trans. Archit. Code Optim. 1(2): 152-179 (2004) - [j5]Tali Moreshet, R. Iris Bahar:
Effects of speculation on performance and issue queue design. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1123-1126 (2004) - [c21]Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein:
RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI 2004: 407-412 - [c20]Yu Bai, R. Iris Bahar:
Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. ICCD 2004: 54-57 - [c19]Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss:
Fetch Halting on Critical Load Misses. ICCD 2004: 244-249 - 2003
- [c18]Eric Chi, A. Michael Salem, R. Iris Bahar, Richard S. Weiss:
Combining Software and Hardware Monitoring for Improved Power and Performance Tuning. Interaction between Compilers and Computer Architectures 2003: 57-64 - [c17]Tali Moreshet, R. Iris Bahar:
Power-aware issue queue design for speculative instructions. DAC 2003: 634-637 - [c16]R. Iris Bahar, Joseph L. Mundy, Jie Chen:
A Probabilistic-Based Design Methodology for Nanoscale Computation. ICCAD 2003: 480-486 - [c15]Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein:
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. ICCD 2003: 70-75 - [c14]Yu Bai, R. Iris Bahar:
A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. ISVLSI 2003: 139-148 - 2002
- [c13]Hui-Yuan Song, R. Iris Bahar, Joel Grodstein:
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS 2002: 203-208 - 2001
- [c12]R. Iris Bahar, Srilatha Manne:
Power and energy reduction via pipeline balancing. ISCA 2001: 218-229 - 2000
- [j4]R. Iris Bahar, Ernest T. Lampe, Enrico Macii:
Power optimization of technology-dependent circuits based on symbolic computation of logic implications. ACM Trans. Design Autom. Electr. Syst. 5(3): 267-293 (2000) - [c11]Roberto Maro, Yu Bai, R. Iris Bahar:
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. PACS 2000: 97-111
1990 – 1999
- 1999
- [j3]R. Iris Bahar, Brad Calder, Dirk Grunwald:
A comparison of software code reordering and victim buffers. SIGARCH Comput. Archit. News 27(1): 51-54 (1999) - [c10]Brian R. Fisk, R. Iris Bahar:
The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. ICCD 1999: 538-545 - 1998
- [c9]R. Iris Bahar, Gianluca Albera, Srilatha Manne:
Power and performance tradeoffs using various caching strategies. ISLPED 1998: 64-69 - 1997
- [j2]R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Algebraic Decision Diagrams and Their Applications. Formal Methods Syst. Des. 10(2/3): 171-206 (1997) - [j1]R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi:
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1101-1115 (1997) - 1996
- [c8]R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi:
Symbolic computation of logic implications for technology-dependent low-power synthesis. ISLPED 1996: 163-168 - 1995
- [c7]Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino:
Computing the Maximum Power Cycles of a Sequential Circuit. DAC 1995: 23-28 - [c6]R. Iris Bahar, Fabio Somenzi:
Boolean techniques for low power driven re-synthesis. ICCAD 1995: 428-432 - [c5]Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi:
CMOS dynamic power estimation based on collapsible current source transistor modeling. ISLPD 1995: 111-116 - 1994
- [c4]R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi:
Timing Analysis of Combinational Circuits using ADD's. EDAC-ETC-EUROASIC 1994: 625-629 - [c3]R. Iris Bahar, Gary D. Hachtel, Abelardo Pardo, Massimo Poncino, Fabio Somenzi:
An ADD-based algorithm for shortest path back-tracing of large graphs. Great Lakes Symposium on VLSI 1994: 248-251 - [c2]R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi:
A symbolic method to reduce power consumption of circuits containing false paths. ICCAD 1994: 368-371 - 1993
- [c1]R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Algebraic decision diagrams and their applications. ICCAD 1993: 188-191
Coauthor Index
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