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ORCIDAbdulkadir Utku Diril
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2000 – 2009
- 2008
[j5]Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
:
Performance-Optimized Design for Parametric Reliability. J. Electron. Test. 24(1-3): 129-141 (2008)- 2007
- [j4]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee:
Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption. J. Low Power Electron. 3(1): 78-95 (2007) - [c11]Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril:
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. VLSI Design 2007: 711-716 - [i1]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee:
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. CoRR abs/0710.4720 (2007) - 2006
- [j3]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 514-524 (2006) - [c10]Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka:
Adaptive Design for Performance-Optimized Robustness. DFT 2006: 3-11 - 2005
- [j2]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Pseudo Dual Supply Voltage Domino Logic Design. J. Low Power Electron. 1(2): 145-152 (2005) - [j1]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1103-1107 (2005) - [c9]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Low-power domino circuits using NMOS pull-up on off-critical paths. ASP-DAC 2005: 533-538 - [c8]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee:
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. DATE 2005: 288-293 - [c7]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra:
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. IOLTS 2005: 35-40 - [c6]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. VLSI Design 2005: 159-164 - [c5]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. VTS 2005: 298-303 - 2004
- [c4]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Sizing CMOS Circuits for Increased Transient Error Tolerance. IOLTS 2004: 11-16 - [c3]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Low-power dual Vth pseudo dual Vdd domino circuits. SBCCI 2004: 273-277 - 2003
- [c2]Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee:
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. ICCAD 2003: 693-700 - [c1]Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee:
An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs. ISVLSI 2003: 173-182
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