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2010 – 2019
- 2016
[j5]Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier:
Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim. J. Circuits Syst. Comput. 25(3): 1640018:1-1640018:14 (2016)- 2015
- [c28]Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier:
TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. DDECS 2015: 3-8 - 2010
- [c27]Shehzad Hasan
, Ajoy Kumar Palit, Walter Anheier:
Fault diagnosis of crosstalk induced glitches and delay faults. DDECS 2010: 358-363 - [c26]Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier:
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. VLSI Design 2010: 345-350 - [p2]Ajoy Kumar Palit, Walter Anheier:
Efficient Training Algorithm for Neuro-Fuzzy Network and its Application to Nonlinear Sensor Characteristic Linearization. Intelligent Systems for Automated Learning and Adaptation 2010: 72-90
2000 – 2009
- 2009
- [c25]Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler:
Timing Arc based logic analysis for false noise reduction. ICCAD 2009: 225-230 - [p1]Ajoy Kumar Palit, Walter Anheier, Dobrivoje Popovic:
Electrical Load Forecasting Using a Neural-Fuzzy Approach. Natural Intelligence for Scheduling, Planning and Packing Problems 2009: 145-173 - 2008
- [j4]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Crosstalk fault modeling in defective pair of interconnects. Integr. 41(1): 27-37 (2008) - [c24]Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler:
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED 2008: 508-513 - 2007
- [c23]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. DDECS 2007: 161-164 - 2006
- [c22]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. DFT 2006: 336-344 - [c21]Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier:
Reduction of Crosstalk Pessimism using Tendency Graph Approach. ICCD 2006: 50-55 - [c20]Sascha Kneip, Walter Anheier:
Vergleich und Optimierung von Algorithmen zur Modulo-Multiplikation auf Smartcards. MBMV 2006: 292-301 - [c19]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Modeling of Crosstalk Fault in Defective Interconnects. PATMOS 2006: 340-349 - 2005
- [c18]Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel:
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium 2005: 22-27 - [c17]Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel:
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. VLSI Design 2005: 354-359 - 2004
- [c16]Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel:
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. DFT 2004: 174-182 - 2002
- [c15]Ajoy Kumar Palit, Gerhard Doeding, Walter Anheier, Dobrivoje Popovic:
Backpropagation based training algorithm for Takagi-Sugeno type MIMO neuro-fuzzy network to forecast electrical load time series. FUZZ-IEEE 2002: 86-91 - [c14]Volker Meyer, Walter Anheier, Arne Sticht:
Non-robust delay test pattern enhancement. ICECS 2002: 453-456 - 2001
- [c13]Michael Fischell, Walter Anheier:
Investigations of on-line/off-line tests for sensors. ICECS 2001: 117-120 - [c12]Badreddine Rejeb, Heiko Henkelmann, Walter Anheier:
Integer division in residue number system. ICECS 2001: 259-262 - [c11]Volker Meyer, Walter Anheier, Arne Sticht:
Non-robust delay test pattern generation based on stuck-at TPG. ICECS 2001: 1007-1010 - 2000
- [j3]A. Schubert, Walter Anheier:
On Random Pattern Testability of Cryptographic VLSI Cores. J. Electron. Test. 16(3): 185-192 (2000)
1990 – 1999
- 1999
- [j2]Frank Poehl, Walter Anheier:
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. J. Electron. Test. 14(1-2): 49-55 (1999) - [c10]A. Schubert, Walter Anheier:
On random pattern testability of cryptographic VLSI cores. ETW 1999: 15-20 - [c9]Heiko Henkelmann, Walter Anheier:
Implementation of sign detection in RNS using mixed radix representation. ICECS 1999: 323-326 - [c8]A. Schubert, Walter Anheier:
Efficient VLSI implementation of modern symmetric block ciphers. ICECS 1999: 757-760 - [c7]Heiko Henkelmann, C. Bruennlein, Walter Anheier:
Effiziente Methoden zum Zahlenvergleich und zur Vorzeichenerkennung in Restklassensystemen. MBMV 1999: 121-130 - 1998
- [c6]Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar:
A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. VLSI Design 1998: 122-127 - 1997
- [c5]Ansgar Drolshagen, Heiko Henkelmann, Walter Anheier:
Processor Elements for the Standard Cell Implementation of Residue Number Systems. ASAP 1997: 116-123 - 1995
- [c4]Stefan Radtke, Jens Bargfrede, Walter Anheier:
Distributed automatic test pattern generation with a parallel FAN algorithm. ICCD 1995: 698-702 - 1994
- [j1]Norbert Ebi, Bernd Lauterbach, Walter Anheier:
An image analysis system for automatic data acquisition from colored scanned maps. Mach. Vis. Appl. 7(3): 148-164 (1994) - [c3]Beom-Ik Cheon, Walter Anheier, Rainer Laur:
A New Strategy for Test Pattern Generation in Sequential Circuits. ISCAS 1994: 77-80 - [c2]Bernd Lauterbach, Walter Anheier:
Segmentation of Scanned Maps in Uniform Color Spaces. MVA 1994: 222-225 - 1993
- [c1]B. Lauerbach, Walter Anheier:
Segmentierung farbiger kartographischer Vorlagen in empfindungsgemäßen Farbräumen. DAGM-Symposium 1993: 733-740
Coauthor Index
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