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ORCIDDaniel Ziener
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- affiliation: University of Erlangen-Nuremberg, Germany
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2020 – today
- 2024
[c34]Ali Asghar
, Andreas Becher, Daniel Ziener:
Short Paper: Analysis of Vivado implementation strategies regarding side-channel leakage for FPGA-based AES implementations. HASP@MICRO 2024: 45-49- 2022
- [c33]Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener:
Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. ARCS 2022: 132-147 - 2021
- [c32]Ali Asghar, Benjamin Hettwer, Emil Karimov, Daniel Ziener:
Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration. ARC 2021: 173-187 - [c31]Hasan Irmak, Daniel Ziener, Nikolaos Alachiotis:
Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration. FPL 2021: 306-311 - [c30]Hasan Irmak, Nikolaos Alachiotis, Daniel Ziener:
An Energy-Efficient FPGA-based Convolutional Neural Network Implementation. SIU 2021: 1-4 - 2020
- [c29]Pepijn de Vos, Michael Kirchhoff, Daniel Ziener:
A Complete Open Source Design Flow for Gowin FPGAs. FPT 2020: 182-189
2010 – 2019
- 2019
- [c28]Ali Asghar, Rick van Loo, Timon Kruiper, Daniel Ziener:
Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining. FPT 2019: 351-354 - 2018
- [j6]Thorbjörn Posewsky, Daniel Ziener:
Throughput optimizations for FPGA-based deep neural network inference. Microprocess. Microsystems 60: 151-161 (2018) - [c27]Thorbjörn Posewsky, Daniel Ziener:
A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks. ARCS 2018: 311-323 - [c26]Daniel Ziener, Jutta Pirkl, Jürgen Teich:
Configuration Tampering of BRAM-based AES Implementations on FPGAs. ReConFig 2018: 1-7 - [i6]Daniel Ziener:
Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems. CoRR abs/1809.11156 (2018) - [i5]Thorbjörn Posewsky, Daniel Ziener:
Throughput Optimizations for FPGA-based Deep Neural Network Inference. CoRR abs/1810.00722 (2018) - 2017
- [b2]Daniel Michael Ziener:
Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems. University of Erlangen-Nuremberg, Germany, 2017 - [j5]Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner:
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. Integr. 59: 98-108 (2017) - [i4]Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner:
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. CoRR abs/1707.08134 (2017) - 2016
- [j4]Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber:
FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Trans. Reconfigurable Technol. Syst. 9(4): 25:1-25:24 (2016) - [c25]Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich:
A LUT-Based Approximate Adder. FCCM 2016: 27 - [c24]Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener:
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT 2016: 213-216 - [c23]Thorbjörn Posewsky, Daniel Ziener:
Efficient deep neural network acceleration through FPGA-based batch processing. ReConFig 2016: 1-8 - [p1]Dirk Koch, Daniel Ziener, Frank Hannig:
FPGA Versus Software Programming: Why, When, and How? FPGAs for Software Programmers 2016: 1-21 - [e1]Dirk Koch, Frank Hannig, Daniel Ziener:
FPGAs for Software Programmers. Springer 2016, ISBN 978-3-319-26406-6 [contents] - 2015
- [c22]Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger:
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. AHS 2015: 1-8 - [c21]Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich:
A co-design approach for accelerated SQL query processing via FPGA-based data filtering. FPT 2015: 192-195 - [i3]Frank Hannig, Dirk Koch, Daniel Ziener:
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR abs/1508.06320 (2015) - 2014
- [c20]Robért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener:
A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor. FCCM 2014: 251-258 - [c19]Bernhard Schmidt, Daniel Ziener, Jürgen Teich:
An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). FPGA 2014: 257 - [c18]Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich:
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. FPL 2014: 1-8 - [c17]Bernhard Schmidt, Daniel Ziener, Jürgen Teich:
Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning. IPDPS Workshops 2014: 299-304 - [i2]Frank Hannig, Dirk Koch, Daniel Ziener:
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). CoRR abs/1408.4423 (2014) - 2013
- [j3]Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich:
Symbolic system-level design methodology for multi-mode reconfigurable systems. Des. Autom. Embed. Syst. 17(2): 343-375 (2013) - [c16]Christopher Dennl, Daniel Ziener, Jürgen Teich:
Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. FCCM 2013: 25-28 - 2012
- [c15]Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele:
Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops 2012: 297-319 - [c14]Christopher Dennl, Daniel Ziener, Jürgen Teich:
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. FCCM 2012: 45-52 - [c13]Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener:
FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). ReConFig 2012: 1-6 - 2011
- [c12]Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich:
Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS 2011: 129-138 - [c11]Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich:
Stress-Aware Module Placement on Reconfigurable Devices. FPL 2011: 277-281 - [c10]Stefan Wildermann, Jürgen Teich, Daniel Ziener:
Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL 2011: 429-434 - [c9]Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich:
Runtime stress-aware replica placement on reconfigurable devices under safety constraints. FPT 2011: 1-6 - [c8]Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich:
An FPGA implementation of a threat-based strategy for Connect6. FPT 2011: 1-4 - 2010
- [b1]Daniel Ziener:
Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs. University of Erlangen-Nuremberg, 2010, ISBN 978-3-86853-657-7, pp. 1-325 - [c7]Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich:
A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE 2010: 375-380 - [c6]Daniel Ziener, Florian Baueregger, Jürgen Teich:
Using the Power Side Channel of FPGAs for Communication. FCCM 2010: 237-244 - [c5]Daniel Ziener, Florian Baueregger, Jürgen Teich:
Multiplexing Methods for Power Watermarking. HOST 2010: 36-41 - [i1]Daniel Ziener, Jürgen Teich:
New Directions for IP Core Watermarking and Identification. Dynamically Reconfigurable Architectures 2010
2000 – 2009
- 2009
- [j2]Daniel Ziener, Jürgen Teich:
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. Int. J. Auton. Adapt. Commun. Syst. 2(3): 256-275 (2009) - 2008
- [j1]Daniel Ziener, Jürgen Teich:
Power Signature Watermarking of IP Cores for FPGAs. J. Signal Process. Syst. 51(1): 123-136 (2008) - [c4]Daniel Ziener, Jürgen Teich:
Concepts for Autonomous Control Flow Checking for Embedded CPUs. ATC 2008: 234-248 - [c3]Moritz Schmid, Daniel Ziener, Jürgen Teich:
Netlist-level IP protection by watermarking for LUT-based FPGAs. FPT 2008: 209-216 - 2006
- [c2]Daniel Ziener, Stefan Assmus, Jürgen Teich:
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. FPL 2006: 1-6 - [c1]Daniel Ziener, Jürgen Teich:
FPGA core watermarking based on power signature analysis. FPT 2006: 205-212
Coauthor Index
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