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2000 – 2009
- 2004
[j3]Zhipei Chi, Leilei Song, Keshab K. Parhi
:
On The Performance/Complexity Tradeoff in Block Turbo Decoder Design. IEEE Trans. Commun. 52(2): 173-175 (2004)- [j2]Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi:
On the better protection of short-frame turbo codes. IEEE Trans. Commun. 52(9): 1435-1439 (2004) - 2002
- [j1]Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi:
Area-efficient high-speed decoding schemes for turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 902-912 (2002) - [c7]Zhipei Chi, Keshab K. Parhi:
High speed algorithm and VLSI architecture design for decoding BCH product codes. ICASSP 2002: 3089-3092 - [c6]Zhipei Chi, Keshab K. Parhi:
High speed VLSI architecture design for block turbo decoder. ISCAS (1) 2002: 901-904 - 2001
- [c5]Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi:
Area-efficient high speed decoding schemes for turbo/MAP decoders. ICASSP 2001: 2633-2636 - [c4]Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi:
A study on the performance, power consumption tradeoffs of short frame turbo decoder design. ICASSP 2001: 2637-2640 - [c3]Zhipei Chi, Leilei Song, Keshab K. Parhi:
A study on the performance, complexity tradeoffs of block turbo decoder design. ISCAS (4) 2001: 65-68 - 2000
- [c2]Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi:
High throughput low energy FEC/ARQ technique for short frame turbo codes. ICASSP 2000: 2653-2656
1990 – 1999
- 1999
- [c1]Zhipei Chi, Jun Ma, Keshab K. Parhi:
Pipelined QR decomposition based multi-channel least square lattice adaptive filter architectures. ISCAS (3) 1999: 49-53
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