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2020 – today
- 2023
[j37]Joshua R. Bertram, Joseph Zambreno
, Peng Wei:
Efficient Unmanned Aerial Systems Navigation With Collision Avoidance in Dense Urban Environments. IEEE Trans. Intell. Transp. Syst. 24(8): 8163-8173 (2023)- [c82]Benjamin Welte, Joseph Zambreno:
An FPGA Implementation of SipHash. IPDPS Workshops 2023: 63-70 - 2022
- [j36]Uchenna Ezeobi, Habeeb Olufowobi, Clinton Young, Joseph Zambreno, Gedare Bloom:
Reverse Engineering Controller Area Network Messages Using Unsupervised Machine Learning. IEEE Consumer Electron. Mag. 11(1): 50-56 (2022) - [j35]Joshua R. Bertram, Peng Wei, Joseph Zambreno:
A Fast Markov Decision Process-Based Algorithm for Collision Avoidance in Urban Air Mobility. IEEE Trans. Intell. Transp. Syst. 23(9): 15420-15433 (2022) - 2021
- [j34]Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones:
Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. 113: 101896 (2021) - [c81]Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. ASAP 2021: 250-257 - 2020
- [j33]Habeeb Olufowobi, Clinton Young, Joseph Zambreno, Gedare Bloom:
SAIDuCANT: Specification-Based Automotive Intrusion Detection Using Controller Area Network (CAN) Timing. IEEE Trans. Veh. Technol. 69(2): 1484-1494 (2020) - [j32]Saunak Saha, Henry Duwe, Joseph Zambreno:
CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks. J. Signal Process. Syst. 92(9): 907-929 (2020) - [c80]Mohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno:
ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation. ASAP 2020: 185-188 - [c79]Brian Kempa, Pei Zhang, Phillip H. Jones, Joseph Zambreno, Kristin Yvonne Rozier:
Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2. FORMATS 2020: 196-214 - [c78]Clinton Young, Jordan Svoboda, Joseph Zambreno:
Towards Reverse Engineering Controller Area Network Messages Using Machine Learning. WF-IoT 2020: 1-6 - [i2]Joshua R. Bertram, Peng Wei, Joseph Zambreno:
Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict. CoRR abs/2008.03518 (2020)
2010 – 2019
- 2019
- [j31]Clinton Young, Joseph Zambreno, Habeeb Olufowobi, Gedare Bloom:
Survey of Automotive Controller Area Network Intrusion Detection Systems. IEEE Des. Test 36(6): 48-55 (2019) - [c77]Saunak Saha, Henry Duwe, Joseph Zambreno:
An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators. ASAP 2019: 197-205 - [c76]Clinton Young, Habeeb Olufowobi, Gedare Bloom, Joseph Zambreno:
Automotive Intrusion Detection Based on Constant CAN Message Frequencies Across Vehicle Driving Modes. AutoSec@CODASPY 2019: 9-14 - [c75]Habeeb Olufowobi, Uchenna Ezeobi, Eric Muhati, Gaylon Robinson, Clinton Young, Joseph Zambreno, Gedare Bloom:
Anomaly Detection Approach Using Adaptive Cumulative Sum Algorithm for Controller Area Network. AutoSec@CODASPY 2019: 25-30 - [c74]Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers:
Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM 2019: 336 - [c73]Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones:
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS 2019: 1-8 - [i1]Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones:
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR abs/1906.11879 (2019) - 2018
- [j30]Alex Grieve, Michael Davies, Phillip H. Jones, Joseph Zambreno:
ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits. IEEE Trans. Computers 67(8): 1092-1104 (2018) - [c72]Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. FPL 2018: 351-354 - [c71]Xian Zhu, Robert Wernsman, Joseph Zambreno:
Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection. ICPP 2018: 64:1-64:10 - [c70]Joe Avey, Phillip H. Jones, Joseph Zambreno:
An FPGA-based Hardware Accelerator for Iris Segmentation. ReConFig 2018: 1-8 - [c69]Matthew Cauwels, Joseph Zambreno, Phillip H. Jones:
HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. ReConFig 2018: 1-8 - [c68]Habeeb Olufowobi, Gedare Bloom, Clinton Young, Joseph Zambreno:
Work-in-Progress: Real-Time Modeling for Intrusion Detection in Automotive Controller Area Network. RTSS 2018: 161-164 - 2017
- [j29]Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones:
The design and integration of a software configurable and parallelized coprocessor architecture for LQR control. J. Parallel Distributed Comput. 106: 121-131 (2017) - [c67]Pei Zhang, Joseph Zambreno, Phillip H. Jones:
An embedded scalable linear model predictive hardware-based controller using ADMM. ASAP 2017: 176-183 - [c66]Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization. IPDPS Workshops 2017: 106-114 - 2016
- [j28]Chad Nelson, Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno:
RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing. IEEE Trans. Parallel Distributed Syst. 27(10): 3029-3043 (2016) - [j27]Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno:
A Reconfigurable Architecture for the Detection of Strongly Connected Components. ACM Trans. Reconfigurable Technol. Syst. 9(2): 16:1-16:19 (2016) - [c65]Diane T. Rover, Joseph Zambreno, Mani Mina, Phillip H. Jones, Lora Leigh Chrystal:
Evidence-based planning to broaden the participation of women in electrical and computer engineering. FIE 2016: 1-7 - [c64]Xinying Wang, Joseph Zambreno:
Parallelizing Latent Semantic Indexing using an FPGA-based architecture. ICCD 2016: 432-435 - [c63]Xian Zhu, Mihir Awatramani, Diane T. Rover, Joseph Zambreno:
ONAC: Optimal number of active cores detector for energy efficient GPU computing. ICCD 2016: 512-519 - [c62]Aaron Mills, Phillip H. Jones, Joseph Zambreno:
Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling. IPDPS Workshops 2016: 139-147 - 2015
- [j26]Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno:
A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. Int. J. Reconfigurable Comput. 2015: 826283:1-826283:12 (2015) - [j25]Tyler Johnson, Daniel Roggow, Phillip H. Jones, Joseph Zambreno:
An FPGA Architecture for the Recovery of WPA/WPA2 Keys. J. Circuits Syst. Comput. 24(7): 1550105:1-1550105:26 (2015) - [j24]Madhu Monga, Daniel Roggow, Manoj Karkee, Song Sun, Lakshmi Kiran Tondehal, Brian L. Steward, Atul G. Kelkar, Joseph Zambreno:
Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform. Microprocess. Microsystems 39(8): 720-740 (2015) - [j23]Xinying Wang, Phillip H. Jones, Joseph Zambreno:
A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. SIGARCH Comput. Archit. News 43(4): 76-81 (2015) - [c61]Mihir Awatramani, Xian Zhu, Joseph Zambreno, Diane T. Rover:
Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications. PACT 2015: 1-12 - [c60]Kevin R. Townsend, Joseph Zambreno:
A multi-phase approach to floating-point compression. EIT 2015: 251-256 - [c59]Kevin R. Townsend, Song Sun, Tyler Johnson, Osama G. Attia, Phillip H. Jones, Joseph Zambreno:
k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator. EIT 2015: 257-263 - [c58]Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones:
A software configurable coprocessor-based state-space controller. FPL 2015: 1-6 - [c57]Daniel Roggow, Paul Uhing, Phillip H. Jones, Joseph Zambreno:
A project-based embedded systems design course using a reconfigurable SoC platform. MSE 2015: 9-12 - [c56]Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno:
Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. ReConFig 2015: 1-6 - [c55]Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones:
A software configurable and parallelized coprocessor architecture for LQR control. ReConFig 2015: 1-8 - 2014
- [j22]Sudhanshu Vyas, Chetan Kumar Ng, Joseph Zambreno, Christopher D. Gill, Ron Cytron, Phillip H. Jones:
An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis. IEEE Embed. Syst. Lett. 6(1): 4-7 (2014) - [j21]N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Hardware-software architecture for priority queue management in real-time and embedded systems. Int. J. Embed. Syst. 6(4): 319-334 (2014) - [j20]Amit Pande, Shaxun Chen, Prasant Mohapatra, Joseph Zambreno:
Hardware Architecture for Video Authentication Using Sensor Pattern Noise. IEEE Trans. Circuits Syst. Video Technol. 24(1): 157-167 (2014) - [c54]Aaron Mills, Joseph Zambreno:
Towards scalable monitoring and maintenance of rechargeable batteries. EIT 2014: 624-629 - [c53]Xinying Wang, Joseph Zambreno:
An Efficient Architecture for Floating-Point Eigenvalue Decomposition. FCCM 2014: 64-67 - [c52]N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Cache design for mixed criticality real-time systems. ICCD 2014: 513-516 - [c51]Mihir Awatramani, Joseph Zambreno, Diane T. Rover:
Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications. ICPP Workshops 2014: 1-8 - [c50]Xinying Wang, Joseph Zambreno:
An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition. IPDPS Workshops 2014: 220-227 - [c49]Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno:
CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search. IPDPS Workshops 2014: 228-235 - [c48]Xinying Wang, Phillip H. Jones, Joseph Zambreno:
A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach. ISVLSI 2014: 541-546 - [c47]Kevin Townsend, Phillip H. Jones, Joseph Zambreno:
A high performance systolic architecture for k-NN classification. MEMOCODE 2014: 201-204 - 2013
- [j19]Amit Pande, Prasant Mohapatra, Joseph Zambreno:
Securing Multimedia Content Using Joint Compression and Encryption. IEEE Multim. 20(4): 50-61 (2013) - [j18]Sudhanshu Vyas, Adwait Gupte, Christopher D. Gill, Ron K. Cytron, Joseph Zambreno, Phillip H. Jones:
Hardware architectural support for control systems and sensor processing. ACM Trans. Embed. Comput. Syst. 13(2): 16:1-16:25 (2013) - [j17]Amit Pande, Joseph Zambreno:
A chaotic encryption scheme for real-time embedded systems: design and implementation. Telecommun. Syst. 52(2): 551-561 (2013) - [c46]Kevin Townsend, Joseph Zambreno:
Reduce, Reuse, Recycle (R3): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms. ASAP 2013: 185-191 - [c45]Amar Krishna, Joseph Zambreno, Sandeep Krishnan:
Polarity Trend Analysis of Public Sentiment on YouTube. COMAD 2013: 125-128 - [c44]Chetan Kumar Ng, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. ICCS 2013: 1891-1898 - [c43]Mihir Awatramani, Joseph Zambreno, Diane T. Rover:
Increasing GPU throughput using kernel interleaved thread block scheduling. ICCD 2013: 503-506 - [c42]Michael Patterson, Aaron Mills, Ryan A. Scheel, Julie Tillman, Evan Dye, Joseph Zambreno:
A multi-faceted approach to FPGA-based Trojan circuit detection. VTS 2013: 1-4 - 2012
- [b1]Amit Pande, Joseph Zambreno:
Embedded Multimedia Security Systems - Algorithms and Architectures. Springer 2012, ISBN 978-1-4471-4458-8, pp. I-XVII, 1-146 - [j16]Amit Pande, Joseph Zambreno:
The secure wavelet transform. J. Real Time Image Process. 7(2): 131-142 (2012) - [j15]Song Sun, Madhu Monga, Phillip H. Jones, Joseph Zambreno:
An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 113-123 (2012) - [j14]Amit Pande, Joseph Zambreno:
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression. ACM Trans. Embed. Comput. Syst. 11(1): 6:1-6:26 (2012) - [c41]Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno:
Design and evaluation of a delay-based FPGA Physically Unclonable Function. ICCD 2012: 143-146 - [c40]Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno:
Shepard: A fast exact match short read aligner. MEMOCODE 2012: 91-94 - [c39]Madhu Monga, Manoj Karkee, Song Sun, Lakshmi Kiran Tondehal, Brian L. Steward, Atul G. Kelkar, Joseph Zambreno:
Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform. ICCS 2012: 338-347 - [c38]Chetan Kumar Ng, Sudhanshu Vyas, Jonathan A. Shidal, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Improving System Predictability and Performance via Hardware Accelerated Data Structures. ICCS 2012: 1197-1205 - 2011
- [j13]Amit Pande, Joseph Zambreno:
Efficient mapping and acceleration of AES on custom multi-core architectures. Concurr. Comput. Pract. Exp. 23(4): 372-389 (2011) - [j12]Alex Baumgarten, Michael Steffen, Matthew Clausman, Joseph Zambreno:
A case study in hardware Trojan design and implementation. Int. J. Inf. Sec. 10(1): 1-14 (2011) - [j11]Song Sun, Joseph Zambreno:
Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining. IEEE Trans. Parallel Distributed Syst. 22(9): 1497-1505 (2011) - [c37]Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno:
Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. ICCD 2011: 289-292 - [c36]Amit Pande, Prasant Mohapatra, Joseph Zambreno:
Using Chaotic Maps for Encrypting Image and Video Content. ISM 2011: 171-178 - [c35]Amit Pande, Joseph Zambreno, Prasant Mohapatra:
Architectures for Simultaneous Coding and Encryption Using Chaotic Maps. ISVLSI 2011: 351-352 - [c34]Michael Steffen, Phillip H. Jones, Joseph Zambreno:
Teaching graphics processing and architecture using a hardware prototyping approach. MSE 2011: 13-16 - 2010
- [j10]Alex Baumgarten, Akhilesh Tyagi, Joseph Zambreno:
Preventing IC Piracy Using Reconfigurable Logic Barriers. IEEE Des. Test Comput. 27(1): 66-75 (2010) - [j9]Amit Pande, Joseph Zambreno:
Reconfigurable hardware implementation of a modified chaotic filter bank scheme. Int. J. Embed. Syst. 4(3/4): 248-258 (2010) - [c33]Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
Detecting/preventing information leakage on the memory bus due to malicious hardware. DATE 2010: 861-866 - [c32]Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno:
CANSCID-CUDA. MEMOCODE 2010: 95-98 - [c31]Michael Steffen, Joseph Zambreno:
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels. MICRO 2010: 237-248 - [c30]Michael Steffen, Joseph Zambreno:
A hardware pipeline for accelerating ray traversal algorithms on streaming processors. SASP 2010: 22-29 - [c29]Amit Pande, Joseph Zambreno:
A Reconfigurable Architecture for Secure Multimedia Delivery. VLSI Design 2010: 258-263
2000 – 2009
- 2009
- [j8]Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno:
Providing secure execution environments with a last line of defense against Trojan circuit attacks. Comput. Secur. 28(7): 660-669 (2009) - [j7]Song Sun, Zijun Yan, Joseph Zambreno:
Demonstrable differential power analysis attacks on real-world FPGA-based embedded systems. Integr. Comput. Aided Eng. 16(2): 119-130 (2009) - [c28]Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno:
Hardware-enforced fine-grained isolation of untrusted code. SecuCode@CCS 2009: 11-18 - [c27]Jesse Sathre, Alex Baumgarten, Joseph Zambreno:
Architectural Support for Automated Software Attack Detection, Recovery, and Prevention. CSE (2) 2009: 254-261 - [c26]Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno:
Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems. CSE (2) 2009: 830-836 - [c25]Amit Pande, Joseph Zambreno:
Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores. CSE (2) 2009: 915-920 - [c24]Amit Pande, Joseph Zambreno:
An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform. ISVLSI 2009: 85-90 - [c23]Michael Steffen, Joseph Zambreno:
Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure. TPCG 2009: 101-108 - 2008
- [j6]Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
Microarchitectures for Managing Chip Revenues under Process Variations. IEEE Comput. Archit. Lett. 7(1): 5-8 (2008) - [j5]Jesse Sathre, Joseph Zambreno:
Automated software attack recovery using rollback and huddle. Des. Autom. Embed. Syst. 12(3): 243-260 (2008) - [j4]Abhishek Das, David Nguyen, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary:
An FPGA-Based Network Intrusion Detection Architecture. IEEE Trans. Inf. Forensics Secur. 3(1): 118-132 (2008) - [c22]Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary:
An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. DATE 2008: 1160-1165 - [c21]Song Sun, Zijun Yan, Joseph Zambreno:
Experiments in attacking FPGA-based embedded systems using differential power analysis. EIT 2008: 7-12 - [c20]Amit Pande, Joseph Zambreno:
Design and analysis of efficient reconfigurable wavelet filters. EIT 2008: 327-332 - [c19]Song Sun, Joseph Zambreno:
Mining Association Rules with systolic trees. FPL 2008: 143-148 - [c18]Amit Pande, Joseph Zambreno:
Polymorphic wavelet architectures using reconfigurable hardware. FPL 2008: 471-474 - [c17]Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
Evaluating the effects of cache redundancy on profit. MICRO 2008: 388-398 - [c16]Song Sun, Michael Steffen, Joseph Zambreno:
A Reconfigurable Platform for Frequent Pattern Mining. ReConFig 2008: 55-60 - 2007
- [j3]Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
Microarchitectures for Managing Chip Revenues under Process Variations. IEEE Comput. Archit. Lett. 6(2): 29-32 (2007) - [c15]Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno:
Interactive presentation: An FPGA implementation of decision tree classification. DATE 2007: 189-194 - [c14]Sailesh Pati, Ramanathan Narayanan, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno:
Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction. FPT 2007: 49-56 - [c13]Ramanathan Narayanan, Berkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno:
Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads. International Conference on Computational Science (3) 2007: 734-741 - 2006
- [j2]Joseph Zambreno, Daniel Honbo, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari:
High-Performance Software Protection Using Reconfigurable Architectures. Proc. IEEE 94(2): 419-431 (2006) - [c12]Berkin Özisikyilmaz, Ramanathan Narayanan, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary:
An Architectural Characterization Study of Data Mining and Bioinformatics Workloads. IISWC 2006: 61-70 - [c11]Ramanathan Narayanan, Berkin Özisikyilmaz, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary:
MineBench: A Benchmark Suite for Data Mining Workloads. IISWC 2006: 182-188 - 2005
- [j1]Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari, Nasir D. Memon:
SAFE-OPS: An approach to embedded software security. ACM Trans. Embed. Comput. Syst. 4(1): 189-210 (2005) - [c10]Joseph Zambreno, Daniel Honbo, Alok N. Choudhary:
Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures. FCCM 2005: 333-334 - [c9]Olga Gelbart, Paul Ott, Bhagirath Narahari, Rahul Simha, Alok N. Choudhary, Joseph Zambreno:
CODESSEAL: Compiler/FPGA Approach to Secure Applications. ISI 2005: 530-535 - [c8]Kripashankar Mohan, Bhagirath Narahari, Rahul Simha, Paul Ott, Alok N. Choudhary, Joseph Zambreno:
Performance Study of a Compiler/Hardware Approach to Embedded Systems Security. ISI 2005: 543-548 - 2004
- [c7]Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari:
Flexible Software Protection Using Hardware/Software Codesign Techniques. DATE 2004: 636-641 - [c6]Joseph Zambreno, Rahul Simha, Alok N. Choudhary:
Addressing application integrity attacks using a reconfigurable architecture. FPGA 2004: 250 - [c5]Joseph Zambreno, David Nguyen, Alok N. Choudhary:
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. FPL 2004: 575-585 - [c4]David Nguyen, Joseph Zambreno, Gokhan Memik:
Flow Monitoring in High-Speed Networks with 2D Hash Tables. FPL 2004: 1093-1097 - [c3]Joseph Zambreno:
Design and Evaluation of an FPGA Architecture for Software Protection. FPL 2004: 1180 - 2002
- [c2]Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Joseph Zambreno:
Optimizing inter-nest data locality. CASES 2002: 127-135 - [c1]Joseph Zambreno, Mahmut T. Kandemir, Alok N. Choudhary:
Enhancing Compiler Techniques for Memory Energy Optimizations. EMSOFT 2002: 364-381
Coauthor Index
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