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ORCIDMaciej J. Ciesielski
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- affiliation: University of Massachusetts Amherst, USA
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2020 – today
- 2024
[c80]Jiteshri Dasari, Maciej J. Ciesielski:
Combining Formal Verification and Testing for Debugging of Arithmetic Circuits. DATE 2024: 1-6- 2023
- [c79]Jiteshri Dasari, Maciej J. Ciesielski:
Formal Verification of Restoring Dividers made Fast and Simple. DAC 2023: 1-6 - [c78]Maciej J. Ciesielski:
Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the Future. DSD 2023: xxxiv - [c77]Jiteshri Dasari, Maciej J. Ciesielski:
Efficient Formal Verification and Debugging of Arithmetic Divider Circuits. ICCAD 2023: 1-9 - [c76]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Divider Circuits by Hardware Reduction. SMACD 2023: 1-4 - 2022
- [c75]Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari:
Functional Verification of Arithmetic Circuits: Survey of Formal Methods. DDECS 2022: 94-99 - 2020
- [j27]Maciej J. Ciesielski
, Tiankai Su, Atif Yasin, Cunxi Yu:
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1346-1357 (2020) - [c74]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. DATE 2020: 532-537 - [c73]Dinesh D. Narasimharaju, R. S. Suraj Rao, Akshaya Sandeep Waingade, Atif Yasin, Maciej J. Ciesielski:
Dual Approach to Solving SAT in Hardware. DTIS 2020: 1-6 - [c72]Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. ISVLSI 2020: 386-391
2010 – 2019
- 2019
- [j26]Cunxi Yu, Maciej J. Ciesielski:
Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 354-365 (2019) - [c71]Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski:
Spectral approach to verifying non-linear arithmetic circuits. ASP-DAC 2019: 261-267 - [c70]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Integer Dividers: Division by a Constant. ISVLSI 2019: 76-81 - [c69]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Functional Verification of Hardware Dividers using Algebraic Model. VLSI-SoC 2019: 257-262 - [i5]Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski:
Spectral Approach to Verifying Non-linear Arithmetic Circuits. CoRR abs/1901.02950 (2019) - 2018
- [j25]Cunxi Yu, Maciej J. Ciesielski, Alan Mishchenko:
Fast Algebraic Rewriting Based on And-Inverter Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1907-1911 (2018) - [c68]Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski:
Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers. ISCAS 2018: 1-5 - [c67]Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej J. Ciesielski, Giovanni De Micheli:
End-to-End Industrial Study of Retiming. ISVLSI 2018: 203-208 - [c66]Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski:
Rewriting Environment for Arithmetic Circuit Verification. LPAR 2018: 656-666 - [i4]Cunxi Yu, Maciej J. Ciesielski:
Formal Analysis of Galois Field Arithmetics - Parallel Verification and Reverse Engineering. CoRR abs/1802.06870 (2018) - 2017
- [j24]Cunxi Yu, Xiangyu Zhang, Duo Liu, Maciej J. Ciesielski, Daniel E. Holcomb:
Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1647-1659 (2017) - [c65]Cunxi Yu, Maciej J. Ciesielski:
Efficient parallel verification of Galois field multipliers. ASP-DAC 2017: 238-243 - [c64]Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski:
Reverse engineering of irreducible polynomials in GF(2m) arithmetic. DATE 2017: 1558-1563 - [c63]Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski:
Advanced datapath synthesis using graph isomorphism. ICCAD 2017: 424-429 - [c62]Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski:
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. ISVLSI 2017: 415-420 - [i3]Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski:
Advanced Datapath Synthesis using Graph Isomorphism. CoRR abs/1708.09597 (2017) - 2016
- [j23]Cunxi Yu, Walter Brown, Duo Liu, André Rossi, Maciej J. Ciesielski:
Formal Verification of Arithmetic Circuits by Function Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2131-2142 (2016) - [c61]Cunxi Yu, Maciej J. Ciesielski, Mihir Choudhury, Andrew Sullivan:
DAG-aware logic synthesis of datapaths. DAC 2016: 135:1-135:6 - [c60]Cunxi Yu, Maciej J. Ciesielski:
Automatic word-level abstraction of datapath. ISCAS 2016: 1718-1721 - [c59]Cunxi Yu, Maciej J. Ciesielski:
Analyzing Imprecise Adders Using BDDs - A Case Study. ISVLSI 2016: 152-157 - [c58]Cunxi Yu, Maciej J. Ciesielski:
Formal Verification Using Don't-Care and Vanishing Polynomials. ISVLSI 2016: 284-289 - [i2]Cunxi Yu, Maciej J. Ciesielski:
Efficient Parallel Verification of Galois Field Multipliers. CoRR abs/1611.05101 (2016) - [i1]Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski:
Reverse Engineering of Irreducible Polynomials in GF(2^m) Arithmetic. CoRR abs/1612.04588 (2016) - 2015
- [c57]Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi:
Verification of gate-level arithmetic circuits by function extraction. DAC 2015: 52:1-52:6 - [c56]Cunxi Yu, Walter Brown, Maciej J. Ciesielski:
Verification of arithmetic datapath designs using word-level approach - A case study. ISCAS 2015: 1862-1865 - [c55]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli:
Exploiting Circuit Duality to Speed up SAT. ISVLSI 2015: 101-106 - [c54]Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski:
Logic Debugging of Arithmetic Circuits. ISVLSI 2015: 113-118 - 2014
- [c53]Tariq B. Ahmad, Maciej J. Ciesielski:
Fast STA prediction-based gate-level timing simulation. DATE 2014: 1-6 - [c52]Tariq Bashir Ahmad, Maciej J. Ciesielski:
Fast time-parallel C-based event-driven RTL simulation. DDECS 2014: 71-76 - [c51]Maciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi:
Function Extraction from Arithmetic Bit-Level Circuits. ISVLSI 2014: 356-361 - [c50]Tariq B. Ahmad, Maciej J. Ciesielski:
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. ISVLSI 2014: 619-624 - 2013
- [j22]Dusung Kim, Maciej J. Ciesielski, Seiyang Yang:
MULTES: Multilevel Temporal-Parallel Event-Driven Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 845-857 (2013) - [c49]Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier:
FPGA latency optimization using system-level transformations and DFG restructuring. DATE 2013: 1553-1558 - [c48]Maciej J. Ciesielski, Walter Brown, André Rossi:
Arithmetic Bit-Level Verification Using Network Flow Model. Haifa Verification Conference 2013: 327-343 - [c47]Tariq Bashir Ahmad, Maciej J. Ciesielski:
An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads. MTV 2013: 77-82 - 2011
- [j21]Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski:
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electron. 7(4): 471-481 (2011) - [c46]Dusung Kim, Maciej J. Ciesielski, Seiyang Yang:
A new distributed event-driven gate-level HDL simulation by accurate prediction. DATE 2011: 547-550 - [c45]Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang:
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. DATE 2011: 1584-1589 - [c44]Mohamed Abdul Basith, Tariq B. Ahmad, André Rossi, Maciej J. Ciesielski:
Algebraic approach to arithmetic design verification. FMCAD 2011: 67-71 - [c43]Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski:
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design 2011: 304-309 - 2010
- [j20]Maciej J. Ciesielski, Anna Kaminska:
The best constant approximant operators in Lorentz spaces Gammap, w and their applications. J. Approx. Theory 162(9): 1518-1544 (2010) - [c42]Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon:
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. HLDVT 2010: 33-39
2000 – 2009
- 2009
- [j19]Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon:
High-Level Dataflow Transformations Using Taylor Expansion Diagrams. IEEE Des. Test Comput. 26(4): 46-57 (2009) - [j18]Maciej J. Ciesielski, Daniel Gomez-Prado, Qian Ren, Jérémie Guillot, Emmanuel Boutillon:
Optimization of Data-Flow Computations Using Canonical TED Representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1321-1333 (2009) - [c41]Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon:
Optimizing data flow graphs to minimize hardware implementation. DATE 2009: 117-122 - 2008
- [c40]Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang:
A fast two-pass HDL simulation with on-demand dump. ASP-DAC 2008: 422-427 - [c39]Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang:
Temporal parallel gate-level timing simulation. HLDVT 2008: 111-116 - [c38]Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang:
Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design 2008: 487-491 - 2007
- [c37]Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon:
Data-flow transformations using Taylor expansion diagrams. DATE 2007: 455-460 - 2006
- [j17]Maciej J. Ciesielski, Priyank Kalla, Serkan Askar:
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. IEEE Trans. Computers 55(9): 1188-1201 (2006) - [c36]Jérémie Guillot, Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar:
Efficient factorization of DSP transforms using taylor expansion diagrams. DATE 2006: 754-755 - 2005
- [j16]Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski:
Functional test generation based on word-level SAT. J. Syst. Archit. 51(8): 488-511 (2005) - [c35]Zhaojun Wo, Israel Koren, Maciej J. Ciesielski:
An ILP Formulation for Yield-driven Architectural Synthesis. DFT 2005: 12-20 - [c34]Zhaojun Wo, Israel Koren, Maciej J. Ciesielski:
Yield-aware Floorplanning. DSD 2005: 247-253 - [c33]Fei Xin, Maciej J. Ciesielski, Ian G. Harris:
Design validation of behavioral VHDL descriptions for arbitrary fault models. ETS 2005: 156-161 - 2004
- [c32]Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski:
A new state assignment technique for testing and low power. DAC 2004: 510-513 - [c31]Daniel Gomez-Prado, Qian Ren, Serkan Askar, Maciej J. Ciesielski, Emmanuel Boutillon:
Variable ordering for taylor expansion diagrams. HLDVT 2004: 55-59 - [c30]Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski:
Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240 - 2003
- [c29]Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski:
Fast Computation of Data Correlation Using BDDs. DATE 2003: 10122-10129 - [c28]Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski:
Mathematical framework for representing discrete functions as word-level polynomials. HLDVT 2003: 135-139 - 2002
- [j15]Priyank Kalla, Maciej J. Ciesielski:
A comprehensive approach to the partial scan problem using implicitstate enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 810-826 (2002) - [j14]Congguang Yang, Maciej J. Ciesielski:
BDS: a BDD-based logic optimization system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 866-876 (2002) - [j13]Maciej J. Ciesielski, Serkan Askar, Samuel Levitin:
Analytical approach to layout generation of datapath cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1480-1488 (2002) - [c27]Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-289 - [c26]Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin:
High-level design verification using Taylor Expansion Diagrams: first results. HLDVT 2002: 13-17 - 2001
- [j12]Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski:
Strategies for solving the Boolean satisfiability problem using binary decision diagrams. J. Syst. Archit. 47(6): 491-503 (2001) - [c25]Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski:
LPSAT: a unified approach to RTL satisfiability. DATE 2001: 398-402 - [c24]Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor expansion diagrams: a new representation for RTL verification. HLDVT 2001: 70-75 - [c23]Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre:
Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387 - 2000
- [j11]Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski:
Retiming-based factorization for sequential logic optimization. ACM Trans. Design Autom. Electr. Syst. 5(3): 373-398 (2000) - [c22]Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal:
BDS: a BDD-based logic optimization system. DAC 2000: 92-97 - [c21]Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang:
A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. DATE 2000: 232-236 - [c20]Congguang Yang, Maciej J. Ciesielski:
Synthesis for Mixed CMOS/PTl Logic. DATE 2000: 750
1990 – 1999
- 1999
- [c19]Priyank Kalla, Maciej J. Ciesielski:
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. DATE 1999: 638-642 - [c18]Serkan Askar, Maciej J. Ciesielski:
Analytical approach to custom datapath design. ICCAD 1999: 98-101 - [c17]Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal:
BDD Decomposition for Efficient Logic Synthesis. ICCD 1999: 626- - [c16]Durgam Vahia, Maciej J. Ciesielski:
Transistor level placement for full custom datapath cell design. ISPD 1999: 158-163 - 1998
- [j10]Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu:
Wave-pipelining: a tutorial and research survey. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 464-474 (1998) - [c15]Balakrishnan Iyer, Maciej J. Ciesielski:
Reencoding for cycle-time minimization under fixed encoding length. ICCAD 1998: 312-315 - [c14]Priyank Kalla, Maciej J. Ciesielski:
A comprehensive approach to the partial scan problem using implicit state enumeration. ITC 1998: 651-657 - 1997
- [c13]Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga:
Intelligent Simulation for Computer Aided Design of Optical Networks. ONDM 1997: 73-86 - [c12]Priyank Kalla, Maciej J. Ciesielski:
Testability of Sequential Circuits with Multi-Cycle False Path. VTS 1997: 322-328 - 1996
- [c11]Balakrishnan Iyer, Maciej J. Ciesielski:
Metamorphosis: state assignment by retiming and re-encoding. ICCAD 1996: 614-617 - 1995
- [j9]Zafar Hasan, Maciej J. Ciesielski:
FSM Decomposition and Functional Verification of FSM Networks. VLSI Design 3(3-4): 249-265 (1995) - [c10]Zafar Hasan, Maciej J. Ciesielski:
Elimination of multi-cycle false paths by state encoding. ED&TC 1995: 155-161 - 1994
- [c9]Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski:
Forum: Wave-pipelining: Is it Practical? ISCAS 1994: 163-166 - 1993
- [j8]Donald A. Joy, Maciej J. Ciesielski:
Clock period minimization with wave pipelining. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4): 461-472 (1993) - [c8]Zafar Hasan, Maciej J. Ciesielski:
Functional verification and simulation of FSM networks. VTS 1993: 326-332 - 1992
- [j7]Zafar Hasan, David Harrison, Maciej J. Ciesielski:
A Fast Partitioning Method for PLA-Based FPGAs. IEEE Des. Test Comput. 9(4): 34-39 (1992) - [j6]Donald A. Joy, Maciej J. Ciesielski:
Layer assignment for printed circuit boards and integrated circuits. Proc. IEEE 80(2): 311-331 (1992) - [j5]Maciej J. Ciesielski, Seiyang Yang:
PLADE: a two-stage PLA decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 943-954 (1992) - [c7]Maya K. Yajnik, Maciej J. Ciesielski:
Finite State Machine Decomposition Using Multiway Partitioning. ICCD 1992: 320-323 - 1991
- [j4]Seiyang Yang, Maciej J. Ciesielski:
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1): 4-12 (1991) - [c6]Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio:
A Unified Approach to Input-Output Encoding for FSM State Assignment. DAC 1991: 176-181 - [c5]Donald A. Joy, Maciej J. Ciesielski:
Placement for Clock Period Minimization With Multiple Wave Propagation. DAC 1991: 640-643
1980 – 1989
- 1989
- [j3]Maciej J. Ciesielski:
Layer assignment for VLSI interconnect delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(6): 702-707 (1989) - [c4]Seiyang Yang, Maciej J. Ciesielski:
PLA decomposition with generalized decoders. ICCAD 1989: 312-315 - [c3]Maciej J. Ciesielski, Saeyang Yang, Marek A. Perkowski:
Multiple-valued Boolean minimization based on graph coloring. ICCD 1989: 262-265 - 1987
- [j2]Maciej J. Ciesielski, Edwin Kinnen:
Digraph Relaxation for 2-Dimensional Placement of IC Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(1): 55-66 (1987) - 1985
- [j1]Maciej J. Ciesielski:
Two-Dimensional Routing for the Silc Silicon Compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 198-203 (1985) - 1982
- [c2]Maciej J. Ciesielski, Edwin Kinnen:
An analytical method for compacting routing area in integrated circuits. DAC 1982: 30-37 - 1981
- [c1]Maciej J. Ciesielski, Edwin Kinnen:
An optimum layer assignment for routing in ICs and PCBs. DAC 1981: 733-737
Coauthor Index
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