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ORCIDWayne Luk
Wayne W. C. Luk
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- affiliation: Imperial College London, UK
- affiliation: Oxford University, Computing Laboratory, UK
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2020 – today
- 2024
[j153]Zhiqiang Que
, Minghao Zhang, Hongxiang Fan, He Li, Ce Guo, Wayne Luk:
Low Latency Variational Autoencoder on FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(2): 323-333 (2024)- [j152]Kang Gao, Perukrishnen Vytelingum, Stephen Weston, Wayne Luk, Ce Guo:
High-Frequency Financial Market Simulation and Flash Crash Scenarios Analysis: An Agent-Based Modelling Approach. J. Artif. Soc. Soc. Simul. 27(2) (2024) - [j151]Ce Guo, Wayne Luk:
FPGA-Accelerated Sim-to-Real Control Policy Learning for Robotic Arms. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1690-1694 (2024) - [j150]Zhiqiang Que, Hongxiang Fan, Marcus Loo, He Li, Michaela Blott, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics. ACM Trans. Embed. Comput. Syst. 23(2): 17:1-17:28 (2024) - [j149]Shuanglong Liu, Hongxiang Fan, Wayne Luk:
Design of Fully Spectral CNNs for Efficient FPGA-Based Acceleration. IEEE Trans. Neural Networks Learn. Syst. 35(6): 8111-8123 (2024) - [j148]Quan Deng, Qiang Liu, Ming Yuan, Xiaohui Duan, Lin Gan, Jinzhe Yang, Wenlai Zhao, Zhenxiang Zhang, Guiming Wu, Wayne Luk, Haohuan Fu, Guangwen Yang:
Acceleration of Multi-Body Molecular Dynamics With Customized Parallel Dataflow. IEEE Trans. Parallel Distributed Syst. 35(12): 2297-2314 (2024) - [c497]Zehuan Zhang, Matej Genci, Hongxiang Fan, Andreas Wetscherek, Wayne Luk:
Accelerating MRI Uncertainty Estimation with Mask-Based Bayesian Neural Network. ASAP 2024: 107-115 - [c496]Shuang Liang, Yuncheng Lu, Ce Guo, Wayne Luk, Paul H. J. Kelly:
PCQ: Parallel Compact Quantum Circuit Simulation. FCCM 2024: 24-31 - [c495]Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides:
Exploring FPGA designs for MX and beyond. FPL 2024: 304-310 - [c494]Ce Guo, Haoran Wu, Wayne Luk:
Resource-Constraint Bayesian Optimization for Soft Processors on FPGAs. HEART 2024: 27-36 - [c493]Marco Procaccini, Amin Sahebi, Marco Barbone, Wayne Luk, Georgi Gaydadjiev, Roberto Giorgi:
Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions. PARMA-DITAM 2024: 6:1-6:12 - [c492]Wayne Luk:
RAW 2024 Invited Talk-1: Auto-Generating Diverse Heterogeneous Designs. IPDPS (Workshops) 2024: 83 - [c491]Jessica Vandebon, Jose G. F. Coutinho, Wayne Luk:
Auto-Generating Diverse Heterogeneous Designs. IPDPS (Workshops) 2024: 116-123 - [c490]Yuan Li, Jianbin Zhu, Yao Fu, Yu Lei, Toshio Nagata, Ryan Braidwood, Haohuan Fu, Juepeng Zheng, Wayne Luk, Hongxiang Fan:
Circular Reconfigurable Parallel Processor for Edge Computing : Industrial Product ✶. ISCA 2024: 863-875 - [c489]Qianzhou Wang, Zhiqiang Que, Wayne Luk:
Trustworthy Codesign by Verifiable Transformations. ITC-Asia 2024: 1-6 - [i31]Patrick Odagiu, Zhiqiang Que, Javier M. Duarte, Johannes Haller, Gregor Kasieczka, Artur Lobanov, Vladimir Loncar, Wayne Luk, Jennifer Ngadiuba, Maurizio Pierini, Philipp Rincke, Arpita Seksaria, Sioni Summers, Andre Sznajder, Alexander D. Tapper, Thea Klæboe Årrestad:
Sets are all you need: Ultrafast jet classification on FPGAs for HL-LHC. CoRR abs/2402.01876 (2024) - [i30]Philippos Papaphilippou, Wayne Luk:
Efficient Adaptable Streaming Aggregation Engine. CoRR abs/2405.18168 (2024) - [i29]Hao Mark Chen, Wayne Luk, Ka Fai Cedric Yiu, Rui Li, Konstantin Mishchenko, Stylianos I. Venieris, Hongxiang Fan:
Hardware-Aware Parallel Prompt Decoding for Memory-Efficient Acceleration of LLM Inference. CoRR abs/2405.18628 (2024) - [i28]Hao Mark Chen, Liam Castelli, Martin Ferianc, Hongyu Zhou, Shuanglong Liu, Wayne Luk, Hongxiang Fan:
Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA. CoRR abs/2406.14593 (2024) - [i27]Zehuan Zhang, Hongxiang Fan, Hao Mark Chen, Lukasz Dudziak, Wayne Luk:
Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA. CoRR abs/2406.16198 (2024) - [i26]Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides:
Exploring FPGA designs for MX and beyond. CoRR abs/2407.01475 (2024) - [i25]Zehuan Zhang, Matej Genci, Hongxiang Fan, Andreas Wetscherek, Wayne Luk:
Accelerating MRI Uncertainty Estimation with Mask-based Bayesian Neural Network. CoRR abs/2407.05521 (2024) - [i24]Ziyang Jiao, Ce Guo, Wayne Luk:
Optimizing VarLiNGAM for Scalable and Efficient Time Series Causal Discovery. CoRR abs/2409.05500 (2024) - 2023
- [j147]Mahyar Shahsavari, David B. Thomas, Marcel van Gerven, Andrew D. Brown, Wayne Luk:
Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems. Array 20: 100323 (2023) - [j146]Mark Vousden, Jordan Morris, Graeme McLachlan Bragg, Jonathan Beaumont, Ashur Rafiev, Wayne Luk, David B. Thomas, Andrew D. Brown:
Event-based high throughput computing: A series of case studies on a massively parallel softcore machine. IET Comput. Digit. Tech. 17(1): 29-42 (2023) - [j145]Amin Sahebi, Marco Barbone, Marco Procaccini, Wayne Luk, Georgi Gaydadjiev, Roberto Giorgi:
Distributed large-scale graph processing on FPGAs. J. Big Data 10(1): 95 (2023) - [j144]Anna Gausen, Wayne Luk, Ce Guo:
Using Agent-Based Modelling to Evaluate the Impact of Algorithmic Curation on Social Media. ACM J. Data Inf. Qual. 15(1): 2:1-2:24 (2023) - [j143]Yun Liang, Wei Zhang, Stephen Neuendorffer, Wayne Luk:
Special Issue: "AI Acceleration on FPGAs". ACM Trans. Embed. Comput. Syst. 22(6): 89:1-89:3 (2023) - [j142]Hongxiang Fan, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point. IEEE Trans. Neural Networks Learn. Syst. 34(8): 4473-4487 (2023) - [j141]Philippos Papaphilippou, Kentaro Sano, Boma Anantasatya Adhi, Wayne Luk:
Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer. IEEE Trans. Parallel Distributed Syst. 34(5): 1621-1634 (2023) - [j140]Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(1): 4:1-4:26 (2023) - [c488]Ce Guo, Wayne Luk, Alexander Warren, Joshua M. Levine, Peter Brookes:
Co-Design of Algorithm and FPGA Accelerator for Conditional Independence Test. ASAP 2023: 102-109 - [c487]José Gabriel F. Coutinho, Ce Guo, Tim Todman, Wayne Luk:
Exploring Machine Learning Adoption in Customisable Processor Design. ASICON 2023: 1-4 - [c486]Hongxiang Fan, Mark Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk:
When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA. DAC 2023: 1-6 - [c485]Wayne Luk:
Heterogeneous Reconfigurable Accelerators: Trends and Perspectives. DAC 2023: 1-2 - [c484]Ce Guo, Diego Cupello, Wayne Luk, Joshua M. Levine, Alexander Warren, Peter Brookes:
FPGA-Accelerated Causal Discovery with Conditional Independence Test Prioritization. FPL 2023: 182-188 - [c483]Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk:
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration. FPL 2023: 248-252 - [c482]Philippos Papaphilippou, Zhiqiang Que, Wayne Luk:
Efficiently Removing Sparsity for High-Throughput Stream Processing. ICFPT 2023: 244-249 - [c481]Omar Tahir, Wayne Luk, Nicolas Wu:
Extensible Embedded Hardware Description Languages with Compilation, Simulation and Verification. HEART 2023: 1-10 - [c480]Stewart Denholm, Wayne Luk:
Customisable Processing of Neural Networks for FPGAs. HEART 2023: 69-77 - [c479]Kang Gao, Stephen Weston, Perukrishnen Vytelingum, Namid R. Stillman, Wayne Luk, Ce Guo:
Deeper Hedging: A New Agent-based Model for Effective Deep Hedging. ICAIF 2023: 270-278 - [i23]Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk:
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration. CoRR abs/2306.08746 (2023) - [i22]Hongxiang Fan, Hao Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk:
When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA. CoRR abs/2308.06849 (2023) - 2022
- [j139]Bingwei Chen, Haohuan Fu, Wayne Luk, Guangwen Yang:
A fully-customized dataflow engine for 3D earthquake simulation with a complex topography. Sci. China Inf. Sci. 65(5): 1-16 (2022) - [j138]Philippos Papaphilippou, Wayne Luk, Chris Brooks:
FLiMS: A Fast Lightweight 2-Way Merger for Sorting. IEEE Trans. Computers 71(12): 3215-3226 (2022) - [j137]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Miguel R. D. Rodrigues, Wayne Luk:
FPGA-Based Acceleration for Bayesian Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5343-5356 (2022) - [j136]Tim Todman, Wayne Luk:
Custom Instructions for Networked Processor Templates. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3096-3100 (2022) - [j135]Shuanglong Liu, Hongxiang Fan, Martin Ferianc, Xinyu Niu, Huifeng Shi, Wayne Luk:
Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs. IEEE Trans. Neural Networks Learn. Syst. 33(8): 3974-3987 (2022) - [j134]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, Xinyu Niu, Miguel R. D. Rodrigues, Wayne Luk:
Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations. IEEE Trans. Parallel Distributed Syst. 33(12): 3387-3399 (2022) - [j133]Philippos Papaphilippou, Jiuxi Meng, Nadeen Gebara, Wayne Luk:
Hipernetch: High-Performance FPGA Network Switch. ACM Trans. Reconfigurable Technol. Syst. 15(1): 3:1-3:31 (2022) - [j132]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk:
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 227-237 (2022) - [c478]Zhiqiang Que, Marcus Loo, Wayne Luk:
Reconfigurable Acceleration of Graph Neural Networks for Jet Identification in Particle Physics. AICAS 2022: 202-205 - [c477]Markus Rognlien, Zhiqiang Que, José Gabriel F. Coutinho, Wayne Luk:
Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices. ARC 2022: 118-133 - [c476]Bowen P. Y. Kwan, Ce Guo, Wayne Luk, Peiyong Jiang:
Light-Weight Permutation Generator for Efficient Convolutional Neural Network Data Augmentation. ARC 2022: 150-165 - [c475]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. ASP-DAC 2022: 250-255 - [c474]Hongxiang Fan, Ce Guo, Wayne Luk:
Optimizing quantum circuit placement via machine learning. DAC 2022: 19-24 - [c473]Hongxiang Fan, Martin Ferianc, Wayne Luk:
Enabling fast uncertainty estimation: accelerating bayesian transformers via algorithmic and hardware optimizations. DAC 2022: 325-330 - [c472]Stewart Denholm, Wayne Luk:
Mixed-Resource Parallel Processing on FPGAs. FCCM 2022: 1 - [c471]Ce Guo, Wayne Luk:
Accelerating Constraint-Based Causal Discovery by Shifting Speed Bottleneck. FPGA 2022: 169-179 - [c470]Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides:
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. FPL 2022: 235-242 - [c469]Stewart Denholm, Wayne Luk:
A Unified Approach for Managing Heterogeneous Processing Elements on FPGAs. FPL 2022: 270-276 - [c468]Zhiqiang Que, Marcus Loo, Hongxiang Fan, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs. FPL 2022: 327-333 - [c467]Filip Wojcicki, Zhiqiang Que, Alexander D. Tapper, Wayne Luk:
Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments. FPT 2022: 1-8 - [c466]Qianzhou Wang, Yat Wong, Zhiqiang Que, Wayne Luk:
Verifying Hardware Optimizations for Efficient Acceleration. HEART 2022: 17-23 - [c465]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk:
Meta-Programming Design-Flow Patterns for Automating Reusable Optimisations. HEART 2022: 42-50 - [c464]Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas, Mark Vousden, Graeme M. Bragg, Jonny Beaumont, Simon W. Moore, Alex Yakovlev, Ashur Rafiev:
Non-deterministic event brokered computing. HEART 2022: 84-86 - [c463]Stewart Denholm, Wayne Luk:
Maximising Parallel Memory Access for Low Latency FPGA Designs. ISCAS 2022: 1477-1481 - [c462]Ziwei Wang, Zhiqiang Que, Wayne Luk, Hongxiang Fan:
Customizable FPGA-based Accelerator for Binarized Graph Neural Networks. ISCAS 2022: 1968-1972 - [c461]Hongxiang Fan, Thomas Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah:
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. MICRO 2022: 599-615 - [p4]Wayne Luk, Ce Guo:
FPGA-Based Backpropagation Engine for Feed-Forward Neural Networks. Mach. Learn. under Resour. Constraints Vol. 1 (1) 2022: 250-263 - [i21]Hongxiang Fan, Thomas Chun-Pong Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah:
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. CoRR abs/2209.09570 (2022) - [i20]Zhiqiang Que, Marcus Loo, Hongxiang Fan, Michaela Blott, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors. CoRR abs/2209.14065 (2022) - 2021
- [j131]Martin C. W. Leong, Kit-Hang Lee, Bowen P. Y. Kwan, Yui-Lun Ng, Zhiyu Liu, Nassir Navab, Wayne Luk, Ka-Wai Kwok:
Performance-aware programming for intraoperative intensity-based image registration on graphics processing units. Int. J. Comput. Assist. Radiol. Surg. 16(3): 375-386 (2021) - [j130]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk:
In-circuit tuning of deep learning designs. J. Syst. Archit. 118: 102198 (2021) - [j129]Nils Voss, Bastiaan Kwaadgras, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev:
On Predictable Reconfigurable System Design. ACM Trans. Archit. Code Optim. 18(2): 17:1-17:28 (2021) - [j128]Jessica Vandebon, José Gabriel de Figueiredo Coutinho, Wayne Luk, Eriko Nurvitadhi:
Enhancing High-Level Synthesis Using a Meta-Programming Approach. IEEE Trans. Computers 70(12): 2043-2055 (2021) - [j127]Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo:
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms. ACM Trans. Reconfigurable Technol. Syst. 14(3): 12:1-12:21 (2021) - [j126]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk:
Scheduling Hardware-Accelerated Cloud Functions. J. Signal Process. Syst. 93(12): 1419-1431 (2021) - [c460]Lei Fu, Ce Guo, Wayne Luk:
FPGA-accelerated Agent-Based Simulation for COVID-19. AICAS 2021: 1-4 - [c459]Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk:
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. ASAP 2021: 117-124 - [c458]Hongxiang Fan, Martin Ferianc, Miguel Rodrigues, Hongyu Zhou, Xinyu Niu, Wayne Luk:
High-Performance FPGA-based Accelerator for Bayesian Neural Networks. DAC 2021: 1063-1068 - [c457]Shuanglong Liu, Hongxiang Fan, Wayne Luk:
Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA. DATE 2021: 1530-1535 - [c456]Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton:
Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. FCCM 2021: 20-28 - [c455]James Stanley Targett, Wayne Luk, Michael Lange, Olivier Marsden:
Systematically migrating an operational microphysics parameterisation to FPGA technology. FCCM 2021: 69-77 - [c454]Ho-Cheung Ng, Izaak Coleman, Shuanglong Liu, Wayne Luk:
Reconfigurable Acceleration of Short Read Mapping with Biological Consideration. FPGA 2021: 229-239 - [c453]Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk:
Demonstrating custom SIMD instruction development for a RISC-V softcore. FPL 2021: 139 - [c452]Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk:
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions. FPL 2021: 391-397 - [c451]Martin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues:
Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator. FPT 2021: 1-10 - [c450]Philippos Papaphilippou, Kentaro Sano, Boma A. Adhi, Wayne Luk:
Efficient Queue-Balancing Switch for FPGAs. FPT 2021: 1-5 - [c449]Marco Barbone, Bas W. Kwaadgras, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev:
Efficient Table-Based Polynomial on FPGA. ICCD 2021: 374-382 - [c448]Mahyar Shahsavari, David B. Thomas, Andrew D. Brown, Wayne Luk:
Neuromorphic Design Using Reward-based STDP Learning on Event-Based Reconfigurable Cluster Architecture. ICONS 2021: 5:1-5:8 - [c447]Anna Gausen, Wayne Luk, Ce Guo:
Can We Stop Fake News? Using Agent-Based Modelling to Evaluate Countermeasures for Misinformation on Social Media. ICWSM Workshops 2021 - [c446]Tim Todman, Wayne Luk:
Custom enhancements to networked processor templates. ISVLSI 2021: 224-229 - [c445]Marco Barbone, Andreas Wetscherek, Thomas Yung, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev:
Efficient Online 4D Magnetic Resonance Imaging. SBAC-PAD 2021: 177-187 - [i19]Hongxiang Fan, Martin Ferianc, Miguel Rodrigues, Hongyu Zhou, Xinyu Niu, Wayne Luk:
High-Performance FPGA-based Accelerator for Bayesian Neural Networks. CoRR abs/2105.09163 (2021) - [i18]Martin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues:
High-Performance FPGA-based Accelerator for Bayesian Recurrent Neural Networks. CoRR abs/2106.06048 (2021) - [i17]Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk:
Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions. CoRR abs/2106.07456 (2021) - [i16]Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk:
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. CoRR abs/2106.14089 (2021) - [i15]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. CoRR abs/2111.12787 (2021) - [i14]Philippos Papaphilippou, Wayne Luk, Chris Brooks:
FLiMS: a Fast Lightweight 2-way Merge Sorter. CoRR abs/2112.05607 (2021) - 2020
- [j125]Izaak Coleman, Giacomo Corleone, James Arram, Ho-Cheung Ng, Luca Magnani, Wayne Luk:
GeDi: applying suffix arrays to increase the repertoire of detectable SNVs in tumour genomes. BMC Bioinform. 21(1): 45 (2020) - [j124]Lin Gan, Ming Yuan, Jinzhe Yang, Wenlai Zhao, Wayne Luk, Guangwen Yang:
High performance reconfigurable computing for numerical simulation and deep learning. CCF Trans. High Perform. Comput. 2(2): 196-208 (2020) - [j123]Nils Voss, Peter Ziegenhein, Lukas Vermond, Joost Hoozemans, Oskar Mencer, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev:
Towards Real Time Radiotherapy Simulation. J. Signal Process. Syst. 92(9): 949-963 (2020) - [j122]Zhiqiang Que, Yongxin Zhu, Hongxiang Fan, Jiuxi Meng, Xinyu Niu, Wayne Luk:
Mapping Large LSTMs to FPGAs with Weight Reuse. J. Signal Process. Syst. 92(9): 965-979 (2020) - [c444]Ce Guo, Wayne Luk, Stephen Weston:
Accelerating Simulation for Agent-based Epidemic Models using FPGAs. AICCSA 2020: 1-8 - [c443]Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano, Wayne Luk:
Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks. ARC 2020: 3-13 - [c442]Jiuxi Meng, Ce Guo, Nadeen Gebara, Wayne Luk:
Fast and Accurate Training of Ensemble Models with FPGA-based Switch. ASAP 2020: 81-84 - [c441]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik:
SLATE: Managing Heterogeneous Cloud Functions. ASAP 2020: 141-148 - [c440]Hiroki Nakahara, Zhiqiang Que, Wayne Luk:
High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. FCCM 2020: 1-9 - [c439]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk:
Optimizing Reconfigurable Recurrent Neural Networks. FCCM 2020: 10-18 - [c438]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Tim Todman:
Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies. FCCM 2020: 177-185 - [c437]Philippos Papaphilippou, Jiuxi Meng, Wayne Luk:
High-Performance FPGA Network Switch Architecture. FPGA 2020: 76-85 - [c436]Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk:
R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. FPGA 2020: 319 - [c435]Nils Voss, Tobias Becker, Simon Tilbury, Georgi Gaydadjiev, Oskar Mencer, Anna Maria Nestorov, Enrico Reggiani, Wayne Luk:
Performance Portable FPGA Design. FPGA 2020: 324 - [c434]Philippos Papaphilippou, Chris Brooks, Wayne Luk:
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. FPL 2020: 65-72 - [c433]Hongxiang Fan, Martin Ferianc, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search. ICCD 2020: 465-468 - [c432]Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT 2020: 20-28 - [c431]Shuanglong Liu, Wayne Luk:
Optimizing Fully Spectral Convolutional Neural Networks on FPGA. FPT 2020: 39-47 - [c430]Ce Guo, Wayne Luk:
Quantisation-aware Dimensionality Reduction. FPT 2020: 237-240 - [c429]Ho-Cheung Ng, Shuanglong Liu, Izaak Coleman, Ringo S. W. Chu, Man-Chung Yue, Wayne Luk:
Acceleration of Short Read Alignment with Runtime Reconfiguration. FPT 2020: 256-262 - [c428]Tim Todman, David B. Thomas, Wayne Luk:
Exploring performance enhancement of event-driven processor networks. FPT 2020: 300 - [c427]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk:
Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs. FPT 2020: 301 - [c426]Ruizhe Zhao, Brian Vogel, Tanvir Ahmed, Wayne Luk:
Reducing Underflow in Mixed Precision Training by Gradient Scaling. IJCAI 2020: 2922-2928 - [c425]Ruizhe Zhao, Wayne Luk, Chao Xiong, Xinyu Niu, Kuen Hung Tsoi:
On the challenges in programming mixed-precision deep neural networks. MAPL@PLDI 2020: 20-28 - [i13]Yang Chu, Wayne Luk, Dan Goodman:
Learning Absolute Sound Source Localisation With Limited Supervisions. CoRR abs/2001.10605 (2020) - [i12]Seyedeh Niusha Alavi Foumani, Ce Guo, Wayne Luk:
An FPGA Accelerated Method for Training Feed-forward Neural Networks Using Alternating Direction Method of Multipliers and LSMR. CoRR abs/2009.02784 (2020) - [i11]Seyedeh Niusha Alavi Foumani, Ce Guo, Wayne Luk:
An Analysis of Alternating Direction Method of Multipliers for Feed-forward Neural Networks. CoRR abs/2009.02825 (2020)
2010 – 2019
- 2019
- [j121]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52(2): 40:1-40:39 (2019) - [j120]Weijia Li, Conghui He, Haohuan Fu, Juepeng Zheng, Runmin Dong, Maocai Xia, Le Yu, Wayne Luk:
A Real-Time Tree Crown Detection Approach for Large-Scale Remote Sensing Images on FPGAs. Remote. Sens. 11(9): 1025 (2019) - [j119]Jingheng Xu, Haohuan Fu, Wen Shi, Lin Gan, Yuxuan Li, Wayne Luk, Guangwen Yang:
Performance Tuning and Analysis for Stencil-Based Applications on POWER8 Processor. ACM Trans. Archit. Code Optim. 15(4): 41:1-41:25 (2019) - [j118]Jingheng Xu, Guangwen Yang, Haohuan Fu, Wayne Luk, Lin Gan, Wen Shi, Wei Xue, Chao Yang, Yong Jiang, Conghui He:
Optimizing Finite Volume Method Solvers on Nvidia GPUs. IEEE Trans. Parallel Distributed Syst. 30(12): 2790-2805 (2019) - [c424]Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk:
Optimizing CNN-Based Hyperspectral Image Classification on FPGAs. ARC 2019: 17-31 - [c423]Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk:
F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition. ASAP 2019: 1-8 - [c422]Zhiqiang Que, Thomas Nugent, Shuanglong Liu, Li Tian, Xinyu Niu, Yongxin Zhu, Wayne Luk:
Efficient Weight Reuse for Large LSTMs. ASAP 2019: 17-24 - [c421]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Thomas Chau:
Transparent Heterogeneous Cloud Acceleration. ASAP 2019: 33 - [c420]Ce Guo, Wayne Luk, Stanley Qing Shui Loh, Alexander Warren, Joshua M. Levine:
Customisable Control Policy Learning for Robotics. ASAP 2019: 91-98 - [c419]Nils Voss, Peter Ziegenhein, Lukas Vermond, Joost Hoozemans, Oskar Mencer, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev:
Towards Real Time Radiotherapy Simulation. ASAP 2019: 173-180 - [c418]Jiuxi Meng, Nadeen Gebara, Ho-Cheung Ng, Paolo Costa, Wayne Luk:
Investigating the Feasibility of FPGA-based Network Switches. ASAP 2019: 218-226 - [c417]Ce Guo, Wayne Luk, Wenguang Xu:
Non-linear function evaluation reusing matrix-vector multipliers. ASICON 2019: 1-4 - [c416]Cheng Luo, Man-Kit Sit, Hongxiang Fan, Shuanglong Liu, Wayne Luk, Ce Guo:
Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism. FCCM 2019: 45-52 - [c415]Nils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev:
Memory Mapping for Multi-die FPGAs. FCCM 2019: 78-86 - [c414]Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
On-chip FPGA Debug Instrumentation for Machine Learning Applications. FPGA 2019: 110-115 - [c413]Philippos Papaphilippou, Holger Pirk, Wayne Luk:
Accelerating the Merge Phase of Sort-Merge Join. FPL 2019: 100-105 - [c412]Shuanglong Liu, Wayne Luk:
Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAs. FPL 2019: 187-193 - [c411]Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk:
Towards In-Circuit Tuning of Deep Learning Designs. ICCAD 2019: 1-6 - [c410]Ruizhe Zhao, Wayne Luk:
Efficient Structured Pruning and Architecture Searching for Group Convolution. ICCV Workshops 2019: 1961-1970 - [c409]Hongxiang Fan, Gang Wang, Martin Ferianc, Xinyu Niu, Wayne Luk:
Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGA. FPT 2019: 28-35 - [c408]Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT 2019: 135-143 - [c407]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik:
Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity. FPT 2019: 162-170 - [c406]Zhiqiang Que, Yanyang Liu, Ce Guo, Xinyu Niu, Yongxin Zhu, Wayne Luk:
Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM. FPT 2019: 379-382 - [c405]Ringo S. W. Chu, Ho-Cheung Ng, Xiwei Wang, Wayne Luk:
Convolution Based Spectral Partitioning Architecture for Hyperspectral Image Classification. IGARSS 2019: 3962-3965 - [c404]Nils Voss, Stephen Girdlestone, Tobias Becker, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev:
Low Area Overhead Custom Buffering for FFT. ReConFig 2019: 1-8 - [i10]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR abs/1901.06955 (2019) - [i9]Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk:
Pangloss: a novel Markov chain prefetcher. CoRR abs/1906.00877 (2019) - [i8]Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk:
Optimizing CNN-based Hyperspectral ImageClassification on FPGAs. CoRR abs/1906.11834 (2019) - [i7]Ringo S. W. Chu, Ho-Cheung Ng, Xiwei Wang, Wayne Luk:
Convolution Based Spectral Partitioning Architecture for Hyperspectral Image Classification. CoRR abs/1906.11981 (2019) - 2018
- [j117]Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei:
FP-BNN: Binarized neural network on FPGA. Neurocomputing 275: 1072-1086 (2018) - [j116]Shuanglong Liu, Hongxiang Fan, Xinyu Niu, Ho-Cheung Ng, Yang Chu, Wayne Luk:
Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA. ACM Trans. Reconfigurable Technol. Syst. 11(3): 19:1-19:22 (2018) - [j115]Xitian Fan, Di Wu, Wei Cao, Wayne Luk, Lingli Wang:
Stream Processing Dual-Track CGRA for Object Inference. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1098-1111 (2018) - [j114]Andreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon:
Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies. J. Signal Process. Syst. 90(1): 39-52 (2018) - [c403]Francis P. Russell, James Stanley Targett, Wayne Luk:
From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations. ASAP 2018: 1-8 - [c402]Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas Chau, Alexander Warren, Ben Jeppesen:
Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control. ASAP 2018: 1-8 - [c401]Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Hardware Compilation of Deep Neural Networks: An Overview. ASAP 2018: 1-8 - [c400]Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano:
Performance Prediction for Large-Scale Heterogeneous Platforms. FCCM 2018: 220 - [c399]Ho-Cheung Ng, Shuanglong Liu, Wayne Luk:
ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development. FPGA 2018: 189-198 - [c398]Ruizhe Zhao, Xinyu Niu, Wayne Luk:
Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only). FPGA 2018: 285 - [c397]Shuanglong Liu, Xinyu Niu, Wayne Luk:
A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only. FPGA 2018: 293 - [c396]Philippos Papaphilippou, Wayne Luk:
Accelerating Database Systems Using FPGAs: A Survey. FPL 2018: 125-130 - [c395]Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu:
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. FPL 2018: 147-154 - [c394]Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation. FPL 2018: 287-294 - [c393]Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, Mark Salmon:
CRRS: Custom Regression and Regularisation Solver for Large-Scale Linear Systems. FPL 2018: 389-393 - [c392]Hongxiang Fan, Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu, Xinyu Niu, Wayne Luk:
A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA. FPT 2018: 14-21 - [c391]Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. FPT 2018: 30-37 - [c390]Philippos Papaphilippou, Chris Brooks, Wayne Luk:
FLiMS: Fast Lightweight Merge Sorter. FPT 2018: 78-85 - [c389]Nadeen Gebara, Jiuxi Meng, Wayne Luk, Paolo Costa:
Scheduling Algorithms for High Performance Network Switching on FPGAs: A Survey. FPT 2018: 166-173 - [c388]Bowen P. Y. Kwan, Gary C. T. Chow, Tim Todman, Wayne Luk, Wenguang Xu:
Lossy Multiport Memory. FPT 2018: 250-253 - [c387]Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker:
Performance Estimation for Exascale Reconfigurable Dataflow Platforms. FPT 2018: 314-317 - [c386]Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, Mark Salmon:
CJS: Custom Jacobi Solver. HEART 2018: 9:1-9:6 - [c385]Jürgen Becker, Viktor K. Prasanna, Markus Weimer, Wayne Luk, Kaveh Aasaraai, Derek Chiou:
RAW 2018 Invited Talks. IPDPS Workshops 2018: 81-82 - [c384]Di Wu, Zhanrui Sun, Yongxin Zhu, Li Tian, Hanlin Zhu, Peng Xiong, Zihao Cao, Menglin Wang, Yu Zheng, Chao Xiong, Hao Jiang, Kuen Hung Tsoi, Xinyu Niu, Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng, Wayne Luk:
Custom machine learning architectures: towards realtime anomaly detection for flight testing. IPDPS Workshops 2018: 1323-1330 - [c383]Jiajun Gao, Yongxin Zhu, Meikang Qiu, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk, Ruizhe Zhao, Zhiqiang Que, Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng, Jiayi Chen, Tao Liu:
Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform. SmartCom 2018: 87-96 - [c382]Hanlin Zhu, Yongxin Zhu, Di Wu, Hui Wang, Li Tian, Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng, Jiayi Chen, Tao Liu, Xinyu Niu, Kuen Hung Tsoi, Wayne Luk:
Correlation Coefficient Based Cluster Data Preprocessing and LSTM Prediction Model for Time Series Data in Large Aircraft Test Flights. SmartCom 2018: 376-385 - [i6]Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu:
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. CoRR abs/1809.03318 (2018) - [i5]Ruizhe Zhao, Wayne Luk:
Learning Grouped Convolution for Efficient Domain Adaptation. CoRR abs/1811.09341 (2018) - 2017
- [j113]Lin Gan, Haohuan Fu, Oskar Mencer, Wayne Luk, Guangwen Yang:
Chapter Four - Data Flow Computing in Geoscience Applications. Adv. Comput. 104: 125-158 (2017) - [j112]Thomas Chau, Pavel Burovskiy, Michael J. Flynn, Wayne Luk:
Chapter Two - Advances in Dataflow Systems. Adv. Comput. 106: 21-62 (2017) - [j111]Francis P. Russell, Peter D. Düben, Xinyu Niu, Wayne Luk, Tim N. Palmer:
Exploiting the chaotic behaviour of atmospheric models with reconfigurable architectures. Comput. Phys. Commun. 221: 160-173 (2017) - [j110]Tianrun Li, Thomas Heinis, Wayne Luk:
ADvaNCE - Efficient and Scalable Approximate Density-Based Clustering Based on Hashing. Informatica 28(1): 105-130 (2017) - [j109]Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Guangwen Yang:
Solving Mesoscale Atmospheric Dynamics Using a Reconfigurable Dataflow Architecture. IEEE Micro 37(4): 40-50 (2017) - [j108]Conghui He, Haohuan Fu, Ce Guo, Wayne Luk, Guangwen Yang:
A Fully-Pipelined Hardware Design for Gaussian Mixture Models. IEEE Trans. Computers 66(11): 1837-1850 (2017) - [j107]Eddie Hung, Tim Todman, Wayne Luk:
Transparent In-Circuit Assertions for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1193-1202 (2017) - [j106]James Arram, Thomas Kaplan, Wayne Luk, Peiyong Jiang:
Leveraging FPGAs for Accelerating Short Read Alignment. IEEE ACM Trans. Comput. Biol. Bioinform. 14(3): 668-677 (2017) - [j105]Gordon Inggs, David B. Thomas, Wayne Luk:
A Domain Specific Approach to High Performance Heterogeneous Computing. IEEE Trans. Parallel Distributed Syst. 28(1): 2-15 (2017) - [j104]Pavel Burovskiy, Paul Grigoras, Spencer J. Sherwin, Wayne Luk:
Efficient Assembly for High-Order Unstructured FEM Meshes (FPL 2015). ACM Trans. Reconfigurable Technol. Syst. 10(2): 12:1-12:22 (2017) - [j103]Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang:
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10(2): 15:1-15:17 (2017) - [j102]Jian Yan, Junqi Yuan, Philip Heng Wai Leong, Wayne Luk, Lingli Wang:
Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2842-2855 (2017) - [c381]Andreea-Ingrid Funie, Liucheng Guo, Xinyu Niu, Wayne Luk, Mark Salmon:
Custom Framework for Run-Time Trading Strategies. ARC 2017: 154-167 - [c380]Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk, Qiang Liu:
Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms. ARC 2017: 255-267 - [c379]Paul Grigoras, Pavel Burovskiy, James Arram, Xinyu Niu, Kit Cheung, Junyi Xie, Wayne Luk:
dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs. ARC 2017: 299-310 - [c378]Ruizhe Zhao, Tim Todman, Wayne Luk, Xinyu Niu:
DeepPump: Multi-pumping deep Neural Networks. ASAP 2017: 206 - [c377]Haohuan Fu, Conghui He, Wayne Luk, Weijia Li, Guangwen Yang:
A Nanosecond-Level Hybrid Table Design for Financial Market Data Generators. FCCM 2017: 227-234 - [c376]Haohuan Fu, Conghui He, Huabin Ruan, Itay Greenspon, Wayne Luk, Yongkang Zheng, Junfeng Liao, Qing Zhang, Guangwen Yang:
Accelerating Financial Market Server through Hybrid List Design (Abstract Only). FPGA 2017: 289-290 - [c375]Hongxiang Fan, Xinyu Niu, Qiang Liu, Wayne Luk:
F-C3D: FPGA-based 3-dimensional convolutional neural network. FPL 2017: 1-4 - [c374]Conghui He, Haohuan Fu, Wayne Luk, Weijia Li, Guangen Yang:
Exploring the potential of reconfigurable platforms for order book update. FPL 2017: 1-8 - [c373]Ho-Cheung Ng, Shuanglong Liu, Wayne Luk:
Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts. FPL 2017: 1-8 - [c372]Shengjia Shao, Wayne Luk:
Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation. FPL 2017: 1-6 - [c371]James Stanley Targett, Peter D. Düben, Wayne Luk:
Validating optimisations for chaotic simulations. FPL 2017: 1-4 - [c370]Weijia Li, Conghui He, Haohuan Fu, Wayne Luk:
An FPGA-based tree crown detection approach for remote sensing images. FPT 2017: 231-234 - [c369]Nils Voss, Marco Bacis, Oskar Mencer, Georgi Gaydadjiev, Wayne Luk:
Convolutional Neural Networks on Dataflow Engines. ICCD 2017: 435-438 - [c368]Ruizhe Zhao, Wayne Luk, Xinyu Niu, Huifeng Shi, Haitao Wang:
Hardware Acceleration for Machine Learning. ISVLSI 2017: 645-650 - [c367]Kit-Hang Lee, Martin C. W. Leong, Marco C. K. Chow, Hing-Choi Fu, Wayne Luk, Kam-Yim Sze, Chung-Kwong Yeung, Ka-Wai Kwok:
FEM-based soft robotic control framework for intracavitary navigation. RCAR 2017: 11-16 - [p3]Tim Todman, Wayne Luk:
In-Circuit Assertions and Exceptions for Reconfigurable Hardware Design. Provably Correct Systems 2017: 265-281 - 2016
- [j101]João M. P. Cardoso, José Gabriel F. Coutinho, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Fernando M. Gonçalves:
Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach. Softw. Pract. Exp. 46(2): 251-287 (2016) - [j100]Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk:
An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 178-191 (2016) - [c366]Tianrun Li, Thomas Heinis, Wayne Luk:
Hashing-Based Approximate DBSCAN. ADBIS 2016: 31-45 - [c365]Shaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip H. W. Leong, Yu Peng:
A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification. ARC 2016: 105-116 - [c364]Ben Lindsey, Matthew Leslie, Wayne Luk:
A Domain Specific Language for accelerated Multilevel Monte Carlo simulations. ASAP 2016: 99-106 - [c363]Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang:
F-CNN: An FPGA-based framework for training Convolutional Neural Networks. ASAP 2016: 107-114 - [c362]Teng Yu, Bo Feng, Mark Stillwell, José Gabriel F. Coutinho, Wenlai Zhao, Shuang Liang, Wayne Luk, Alexander L. Wolf, Yuchun Ma:
Relation-oriented resource allocation for multi-accelerator systems. ASAP 2016: 243-244 - [c361]Maciej Kurek, Marc Peter Deisenroth, Wayne Luk, Timothy John Todman:
Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs. FCCM 2016: 84-87 - [c360]Paul Grigoras, Pavel Burovskiy, Wayne Luk:
CASK: Open-Source Custom Architectures for Sparse Kernels. FPGA 2016: 179-184 - [c359]Paul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer J. Sherwin:
Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA. FPL 2016: 1-9 - [c358]Xinyu Niu, Nicholas Ng, Tomofumi Yuki, Shaojun Wang, Nobuko Yoshida, Wayne Luk:
EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits. FPL 2016: 1-4 - [c357]Hao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk:
Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules. FPL 2016: 1-8 - [c356]Shengjia Shao, Oskar Mencer, Wayne Luk:
Dataflow design for optimal incremental SVM training. FPT 2016: 197-200 - [c355]Dirk Stroobandt, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, Xinyu Niu, Dionisios N. Pnevmatikatos, Amit Kulkarni, Elias Vansteenkiste, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Michael Hübner, Tobias Becker, Georgi Gaydadjiev, Antonis Nikitakis, Alex J. W. Thom:
EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures. ReCoSoC 2016: 1-7 - [p2]Xinyu Niu, Tim Todman, Wayne Luk:
Self-adaptive Hardware Acceleration on a Heterogeneous Cluster. Self-aware Computing Systems 2016: 167-192 - [p1]Maciej Kurek, Tobias Becker, Ce Guo, Stewart Denholm, Andreea-Ingrid Funie, Mark Salmon, Tim Todman, Wayne Luk:
Self-aware Hardware Acceleration of Financial Applications on a Heterogeneous Cluster. Self-aware Computing Systems 2016: 241-260 - 2015
- [j99]Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Tobias Becker, Wayne Luk:
Network-Level FPGA Acceleration of Low Latency Market Data Feed Arbitration. IEICE Trans. Inf. Syst. 98-D(2): 288-297 (2015) - [j98]Liucheng Guo, Andreea-Ingrid Funie, Zhongliu Xie, David B. Thomas, Wayne Luk:
A general-purpose framework for FPGA-accelerated genetic algorithms. Int. J. Bio Inspired Comput. 7(6): 361-375 (2015) - [j97]Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Tobias Becker, Peter Böhm, Andreas Brokalakis, Karel Bruneel, Catalin Bogdan Ciobanu, Tom Davidson, Georgi Gaydadjiev, Karel Heyse, Wayne Luk, Xinyu Niu, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman, Elias Vansteenkiste:
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. Microprocess. Microsystems 39(4-5): 321-338 (2015) - [j96]Soukaina N. Hmid, José Gabriel F. Coutinho, Wayne Luk:
A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution. SIGARCH Comput. Archit. News 43(4): 40-45 (2015) - [j95]Liucheng Guo, Andreea-Ingrid Funie, David B. Thomas, Haohuan Fu, Wayne Luk:
Parallel Genetic Algorithms on Multiple FPGAs. SIGARCH Comput. Archit. News 43(4): 86-93 (2015) - [j94]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk:
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 7(4): 36:1-36:17 (2015) - [j93]Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang:
Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable Platforms. ACM Trans. Reconfigurable Technol. Syst. 8(2): 11:1-11:16 (2015) - [j92]Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell:
Automating Elimination of Idle Functions by Runtime Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 8(3): 15:1-15:28 (2015) - [j91]Qiang Liu, Terrence S. T. Mak, Tao Zhang, Xinyu Niu, Wayne Luk, Alex Yakovlev:
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1402-1414 (2015) - [c354]Andreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon:
Reconfigurable acceleration of fitness evaluation in trading strategies. ASAP 2015: 210-217 - [c353]Chao Zhang, Yuchun Ma, Wayne Luk:
HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric. CAD/Graphics 2015: 240-241 - [c352]Catalin Bogdan Ciobanu, Ana Lucia Varbanescu, Dionisios N. Pnevmatikatos, George Charitopoulos, Xinyu Niu, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Muhammed Al Kadi, Michael Hübner, Tobias Becker, Georgi Gaydadjiev, Andreas Brokalakis, Antonis Nikitakis, Alex J. W. Thom, Elias Vansteenkiste, Dirk Stroobandt:
EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing. CSE 2015: 339-342 - [c351]Tim Todman, Stephan Stilkerich, Wayne Luk:
In-circuit temporal monitors for runtime verification of reconfigurable designs. DAC 2015: 50:1-50:6 - [c350]Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk:
Accelerating SpMV on FPGAs by Compressing Nonzero Values. FCCM 2015: 64-67 - [c349]Liucheng Guo, Ce Guo, David B. Thomas, Wayne Luk:
Pipelined Genetic Propagation. FCCM 2015: 103-110 - [c348]Francis P. Russell, Peter D. Düben, Xinyu Niu, Wayne Luk, Tim N. Palmer:
Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic Behaviour. FCCM 2015: 171-178 - [c347]Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk:
Delay-Bounded Routing for Shadow Registers. FPGA 2015: 56-65 - [c346]Xinyu Niu, Wayne Luk, Yu Wang:
EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access. FPGA 2015: 74-83 - [c345]James Arram, Wayne Luk, Peiyong Jiang:
Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment. FPGA 2015: 250-259 - [c344]Pavel Burovskiy, Paul Grigoras, Spencer J. Sherwin, Wayne Luk:
Efficient assembly for high order unstructured FEM meshes. FPL 2015: 1-6 - [c343]Peter Y. K. Cheung, Wayne Luk, Cristina Silvano:
Preface. FPL 2015: 1-2 - [c342]Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang:
Significant papers from the first 25 years of the FPL conference. FPL 2015: 1-3 - [c341]Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston:
Recursive pipelined genetic propagation for bilevel optimisation. FPL 2015: 1-6 - [c340]James Arram, Moritz Pflanzer, Thomas Kaplan, Wayne Luk:
FPGA acceleration of reference-based compression for genomic data. FPT 2015: 9-16 - [c339]James Stanley Targett, Xinyu Niu, Francis P. Russell, Wayne Luk, Stephen Jeffress, Peter D. Düben:
Lower precision for higher accuracy: Precision and resolution exploration for shallow water equations. FPT 2015: 208-211 - [c338]Kit-Hang Lee, Ziyan Guo, Gary C. T. Chow, Yue Chen, Wayne Luk, Ka-Wai Kwok:
GPU-based proximity query processing on unstructured triangular mesh model. ICRA 2015: 4405-4411 - [c337]Jürgen Becker, Ken Eguro, Diana Göhringer, Wayne Luk, Marco D. Santambrogio, Ramachandran Vaidyanathan, Steven J. E. Wilton:
RAW Introduction and Committees. IPDPS Workshops 2015: 68-69 - [c336]Marco Rabozzi, Riccardo Cattaneo, Tobias Becker, Wayne Luk, Marco D. Santambrogio:
Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems. IPDPS Workshops 2015: 97-104 - [i4]Gordon Inggs, David B. Thomas, Wayne Luk:
An Efficient, Automatic Approach to High Performance Heterogeneous Computing. CoRR abs/1505.04417 (2015) - [i3]Gordon Inggs, David B. Thomas, George A. Constantinides, Wayne Luk:
Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service. CoRR abs/1506.06684 (2015) - 2014
- [j90]Tim Todman, Stephan Stilkerich, Wayne Luk:
Using Statistical Assertions to Guide Self-Adaptive Systems. Int. J. Reconfigurable Comput. 2014: 724585:1-724585:8 (2014) - [j89]Yi Shan, Yuchen Hao, Wenqiang Wang, Yu Wang, Xu Chen, Huazhong Yang, Wayne Luk:
Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region. ACM Trans. Embed. Comput. Syst. 13(4s): 132:1-132:24 (2014) - [j88]Xinyu Niu, Qiwei Jin, Wayne Luk, Stephen Weston:
A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 7(2): 15:1-15:19 (2014) - [j87]Adrien Le Masle, Wayne Luk:
Mapping Loop Structures Onto Parametrized Hardware Pipelines. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 631-640 (2014) - [j86]Ce Guo, Wayne Luk:
Pipelined HAC Estimation Engines for Multivariate Time Series. J. Signal Process. Syst. 77(1-2): 117-129 (2014) - [c335]Dionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Georgi Nedeltchev Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt:
Effective Reconfigurable Design: The FASTER Approach. ARC 2014: 318-323 - [c334]José Gabriel F. Coutinho, Oliver Pell, Eoghan O'Neill, Peter Sanders, John McGlone, Paul Grigoras, Wayne Luk, Carmelo Ragusa:
HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform. ARC 2014: 324-329 - [c333]Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Tobias Becker, Wayne Luk:
Low latency FPGA acceleration of market data feed arbitration. ASAP 2014: 36-40 - [c332]Yanhua Li, Youhui Zhang, Jianfeng Yang, Wayne Luk, Guangwen Yang, Weimin Zheng:
An approach of processor core customization for stencil computation. ASAP 2014: 182-183 - [c331]Ce Guo, Wayne Luk, Stephen Weston:
Pipelined reconfigurable accelerator for ordinal pattern encoding. ASAP 2014: 194-201 - [c330]Liucheng Guo, David B. Thomas, Wayne Luk:
Automated Framework for General-Purpose Genetic Algorithms in FPGAs. EvoApplications 2014: 714-725 - [c329]Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk:
SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. FCCM 2014: 141-148 - [c328]Maciej Kurek, Tobias Becker, Thomas C. P. Chau, Wayne Luk:
Automating Optimization of Reconfigurable Designs. FCCM 2014: 210-213 - [c327]Ce Guo, Wayne Luk:
Accelerating parameter estimation for multivariate self-exciting point processes. FPGA 2014: 181-184 - [c326]Pavel Burovskiy, Stephen Girdlestone, Craig Davies, Spencer J. Sherwin, Wayne Luk:
Dataflow acceleration of Krylov subspace sparse banded problems. FPL 2014: 1-6 - [c325]Gary C. T. Chow, Paul Grigoras, Pavel Burovskiy, Wayne Luk:
An efficient sparse conjugate gradient solver using a Beneš permutation network. FPL 2014: 1-7 - [c324]Lin Gan, Haohuan Fu, Chao Yang, Wayne Luk, Wei Xue, Oskar Mencer, Xiaomeng Huang, Guangwen Yang:
A highly-efficient and green data flow engine for solving euler atmospheric equations. FPL 2014: 1-6 - [c323]Liucheng Guo, David B. Thomas, Ce Guo, Wayne Luk:
Automated framework for FPGA-based parallel genetic algorithms. FPL 2014: 1-7 - [c322]Eddie Hung, Tim Todman, Wayne Luk:
Transparent insertion of latency-oblivious logic onto FPGAs. FPL 2014: 1-8 - [c321]Jinzhe Yang, Binghuan Lin, Wayne Luk, Terence Nahar:
Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation. FPL 2014: 1-4 - [c320]Wenlai Zhao, Haohuan Fu, Guangwen Yang, Wayne Luk:
Patra: Parallel tree-reweighted message passing architecture. FPL 2014: 1-6 - [c319]Gordon Inggs, Shane T. Fleming, David B. Thomas, Wayne Luk:
Is high level synthesis ready for business? A computational finance case study. FPT 2014: 12-19 - [c318]Jinzhe Yang, Ce Guo, Wayne Luk, Terence Nahar:
Collaborative processing of Least-Square Monte Carlo for American options. FPT 2014: 52-59 - [c317]Shengjia Shao, Ce Guo, Wayne Luk, Stephen Weston:
Accelerating transfer entropy computation. FPT 2014: 60-67 - [c316]Andrei Bara, Xinyu Niu, Wayne Luk:
A dataflow system for anomaly detection and analysis. FPT 2014: 276-279 - [c315]Yuchun Ma, Jinglan Liu, Chao Zhang, Wayne Luk:
HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs. ICCD 2014: 470-476 - [c314]Andreea-Ingrid Funie, Mark Salmon, Wayne Luk:
A Hybrid Genetic-Programming Swarm-Optimisation Approach for Examining the Nature and Stability of High Frequency Trading Strategies. ICMLA 2014: 29-34 - [c313]Fabrizio Spada, Alberto Scolari, Gianluca C. Durelli, Riccardo Cattaneo, Marco D. Santambrogio, Donatella Sciuto, Dionisios N. Pnevmatikatos, Georgi Gaydadjiev, Oliver Pell, Andreas Brokalakis, Wayne Luk, Dirk Stroobandt, Danilo Pau:
FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board. ISPA 2014: 134-141 - [c312]Paul Grigoras, Max Tottenham, Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk:
Elastic Management of Reconfigurable Accelerators. ISPA 2014: 174-181 - [i2]Gordon Inggs, David B. Thomas, Wayne Luk:
A Domain Specific Approach to Heterogeneous Computing: From Availability to Accessibility. CoRR abs/1408.4965 (2014) - 2013
- [j85]Yuet Ming Lam, Kuen Hung Tsoi, Wayne Luk:
Parallel neighbourhood search on many-core platforms. Int. J. Comput. Sci. Eng. 8(3): 281-293 (2013) - [j84]Simon A. Spacey, Wayne Luk, Daniel Kuhn, Paul H. J. Kelly:
Parallel partitioning for distributed systems using sequential assignment. J. Parallel Distributed Comput. 73(2): 207-219 (2013) - [j83]João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Ricardo Nobre, Razvan Nane, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Koen Bertels:
Controlling a complete hardware synthesis toolchain with LARA aspects. Microprocess. Microsystems 37(8-C): 1073-1089 (2013) - [j82]Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski:
Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Comput. Archit. News 41(5): 35-40 (2013) - [j81]Ce Guo, Wayne Luk, Ekaterina Vinkovskaya, Rama Cont:
Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes. SIGARCH Comput. Archit. News 41(5): 59-64 (2013) - [j80]Liucheng Guo, David B. Thomas, Wayne Luk:
Customisable architectures for the set covering problem. SIGARCH Comput. Archit. News 41(5): 101-106 (2013) - [j79]Ka-Wai Kwok, Kuen Hung Tsoi, Valentina Vitiello, James Clark, Gary C. T. Chow, Wayne Luk, Guang-Zhong Yang:
Dimensionality Reduction in Controlling Articulated Snake Robot for Endoscopy Under Dynamic Active Constraints. IEEE Trans. Robotics 29(1): 15-31 (2013) - [j78]David B. Thomas, Wayne Luk:
The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 761-770 (2013) - [j77]Ying Wang, Xuegong Zhou, Lingli Wang, Jian Yan, Wayne Luk, Chenglian Peng, Jiarong Tong:
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2179-2192 (2013) - [j76]David B. Thomas, Wayne Luk:
Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2193-2205 (2013) - [c311]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski:
Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC 2013: 1-12 - [c310]James Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang:
Hardware Acceleration of Genetic Sequence Alignment. ARC 2013: 13-24 - [c309]Maciej Kurek, Tobias Becker, Wayne Luk:
Parametric Optimization of Reconfigurable Designs Using Machine Learning. ARC 2013: 134-145 - [c308]Paul Grigoras, Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk, Jacob A. Bower, Oliver Pell:
Aspect driven compilation for dataflow designs. ASAP 2013: 18-25 - [c307]Ce Guo, Wayne Luk:
Accelerating HAC estimation for multivariate time series. ASAP 2013: 42-49 - [c306]Alison Eele, Jan M. Maciejowski, Thomas Chau, Wayne Luk:
Parallelisation of Sequential Monte Carlo for real-time control in air traffic management. CDC 2013: 4859-4864 - [c305]Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu:
Automating Elimination of Idle Functions by Run-Time Reconfiguration. FCCM 2013: 97-104 - [c304]James Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang:
Reconfigurable Acceleration of Short Read Mapping. FCCM 2013: 210-217 - [c303]Huabin Ruan, Xiaomeng Huang, Haohuan Fu, Guangwen Yang, Wayne Luk, Sébastien Racanière, Oliver Pell, Wenjing Han:
An FPGA-Based Data Flow Engine for Gaussian Copula Model. FCCM 2013: 218-225 - [c302]Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Guangwen Yang:
Global Atmospheric Simulation on a Reconfigurable Platform. FCCM 2013: 230 - [c301]Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu:
Automating resource optimisation in reconfigurable design (abstract only). FPGA 2013: 275 - [c300]Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang:
Accelerating solvers for global atmospheric equations through mixed-precision data flow engine. FPL 2013: 1-6 - [c299]Ce Guo, Wayne Luk:
Accelerating maximum likelihood estimation for Hawkes point processes. FPL 2013: 1-6 - [c298]Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk:
A scalable design approach for stencil computation on reconfigurable clusters. FPL 2013: 1-4 - [c297]Tim Todman, Wayne Luk:
Runtime assertions and exceptions for streaming systems. FPL 2013: 1-4 - [c296]Thomas C. P. Chau, Ka-Wai Kwok, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk:
Acceleration of real-time Proximity Query for dynamic active constraints. FPT 2013: 206-213 - [c295]Xinyu Niu, José Gabriel F. Coutinho, Yu Wang, Wayne Luk:
Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters. FPT 2013: 214-221 - [c294]Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Wayne Luk:
Application-specific customisation of market data feed arbitration. FPT 2013: 322-325 - [c293]James Arram, Wayne Luk, Peiyong Jiang:
Reconfigurable filtered acceleration of short read alignment. FPT 2013: 438-441 - [c292]Gordon Inggs, David B. Thomas, Wayne Luk:
A Heterogeneous Computing Framework for Computational Finance. ICPP 2013: 688-697 - [c291]Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian:
RALP: Reconvergence-aware layer partitioning for 3D FPGAs. ReConFig 2013: 1-6 - [c290]Riccardo Cattaneo, Xinyu Niu, Christian Pilato, Tobias Becker, Wayne Luk, Marco D. Santambrogio:
A framework for effective exploitation of partial reconfiguration in dataflow computing. ReCoSoC 2013: 1-8 - [c289]Nicholas Ng, Nobuko Yoshida, Wayne Luk:
Scalable Session Programming for Heterogeneous High-Performance Systems. SEFM Workshops 2013: 82-98 - 2012
- [j75]Ka Fai Cedric Yiu, Yao Lu, Chun Hok Ho, Wayne Luk, Jiaquan Huo, Sven Nordholm:
Reconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device. Digit. Signal Process. 22(2): 376-390 (2012) - [j74]Simon A. Spacey, Wolfram Wiesemann, Daniel Kuhn, Wayne Luk:
Robust Software Partitioning with Multiple Instantiation. INFORMS J. Comput. 24(3): 500-515 (2012) - [j73]Simon A. Spacey, Wayne Luk, Paul H. J. Kelly, Daniel Kuhn:
Improving communication latency with the write-only architecture. J. Parallel Distributed Comput. 72(12): 1617-1627 (2012) - [j72]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung:
Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Comput. Archit. News 40(5): 10-15 (2012) - [j71]Kuen Hung Tsoi, Tobias Becker, Wayne Luk:
Modelling reconfigurable systems in event driven simulation. SIGARCH Comput. Archit. News 40(5): 34-39 (2012) - [j70]Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides:
Optimizing Hardware Design by Composing Utility-Directed Transformations. IEEE Trans. Computers 61(12): 1800-1812 (2012) - [j69]Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar:
FISH: Fast Instruction SyntHesis for Custom Processors. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 52-65 (2012) - [j68]Anson H. T. Tse, David B. Thomas, Wayne Luk:
Design Exploration of Quadrature Methods in Option Pricing. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 818-826 (2012) - [j67]Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton:
Optimizing Floating Point Units in Hybrid FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1295-1303 (2012) - [j66]Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides:
Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms. J. Signal Process. Syst. 67(1): 65-78 (2012) - [c288]José Gabriel F. Coutinho, Tiago Carvalho, Sérgio Durand, João M. P. Cardoso, Ricardo Nobre, Pedro C. Diniz, Wayne Luk:
Experiments with the LARA aspect-oriented approach. AOSD (Companion) 2012: 27-30 - [c287]João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Wayne Luk, Ricardo Nobre, Pedro C. Diniz, Zlatko Petrov:
LARA: an aspect-oriented programming language for embedded systems. AOSD 2012: 179-190 - [c286]Qiang Liu, Wayne Luk:
Heterogeneous Systems for Energy Efficient Scientific Computing. ARC 2012: 64-75 - [c285]Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston:
Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations. ARC 2012: 187-201 - [c284]Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk:
Optimising Performance of Quadrature Methods with Reduced Precision. ARC 2012: 251-263 - [c283]Stewart Denholm, Kuen Hung Tsoi, Peter R. Pietzuch, Wayne Luk:
Efficient Communication for FPGA Clusters. ARC 2012: 335-341 - [c282]Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk:
A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration. ASAP 2012: 8-15 - [c281]Tim Todman, Wayne Luk:
Reconfigurable Design Automation by High-Level Exploration. ASAP 2012: 185-188 - [c280]Kyprianos Papadimitriou, Christian Pilato, Dionisios N. Pnevmatikatos, Marco D. Santambrogio, Catalin Bogdan Ciobanu, Tim Todman, Tobias Becker, Tom Davidson, Xinyu Niu, Georgi Gaydadjiev, Wayne Luk, Dirk Stroobandt:
Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration. CSE 2012: 391-398 - [c279]José Gabriel F. Coutinho, Sujit Bhattacharya, Wayne Luk, George A. Constantinides, João M. P. Cardoso, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov:
Resource-Efficient Designs Using an Aspect-Oriented Approach. CSE 2012: 399-406 - [c278]João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk:
Controlling Hardware Synthesis with Aspects. DSD 2012: 226-233 - [c277]Dionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Karel Bruneel, Georgi Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Oliver Pell, Christian Pilato, M. Robart, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman:
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. DSD 2012: 234-241 - [c276]Gary C. T. Chow, Wayne Luk, Philip Heng Wai Leong:
A Mixed Precision Methodology for Mathematical Optimisation. FCCM 2012: 33-36 - [c275]João M. P. Cardoso, João Teixeira, José C. Alves, Ricardo Nobre, Pedro C. Diniz, José Gabriel F. Coutinho, Wayne Luk:
Specifying Compiler Strategies for FPGA-based Systems. FCCM 2012: 192-199 - [c274]Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas:
A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. FPGA 2012: 57-66 - [c273]Adrien Le Masle, Wayne Luk:
Detecting power attacks on reconfigurable hardware. FPL 2012: 14-19 - [c272]Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk:
Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. FPL 2012: 99-104 - [c271]Qiwei Jin, Tobias Becker, Wayne Luk, David B. Thomas:
Optimising explicit finite difference option pricing for dynamic constant reconfiguration. FPL 2012: 165-172 - [c270]Xinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell:
Exploiting run-time reconfiguration in stencil computation. FPL 2012: 173-180 - [c269]Tim Todman, Wayne Luk:
Verification of streaming designs by combining symbolic simulation and equivalence checking. FPL 2012: 203-208 - [c268]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski:
Adaptive Sequential Monte Carlo approach for real-time applications. FPL 2012: 527-530 - [c267]Yi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang, Kuen Hung Tsoi, Wayne Luk, Huazhong Yang:
FPGA based memory efficient high resolution stereo vision system for video tolling. FPT 2012: 29-32 - [c266]Maciej Kurek, Wayne Luk:
Parametric reconfigurable designs with Machine Learning Optimizer. FPT 2012: 109-112 - [c265]Tim Todman, Peter Böhm, Wayne Luk:
Verification of streaming hardware and software codesigns. FPT 2012: 147-150 - [c264]Ce Guo, Haohuan Fu, Wayne Luk:
A fully-pipelined expectation-maximization engine for Gaussian Mixture Models. FPT 2012: 182-189 - [c263]Ying Wang, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong:
A partially reconfigurable architecture supporting hardware threads. FPT 2012: 269-276 - [c262]Kit Cheung, Simon R. Schultz, Wayne Luk:
A Large-Scale Spiking Neural Network Accelerator for FPGA Systems. ICANN (1) 2012: 113-120 - [c261]Xinyu Niu, Kuen Hung Tsoi, Wayne Luk:
Self-Adaptive Heterogeneous Cluster with Wireless Network. IPDPS Workshops 2012: 306-311 - [c260]Yukinori Sato, Yasushi Inoguchi, Wayne Luk, Tadao Nakamura:
Evaluating reconfigurable dataflow computing using the Himeno benchmark. ReConFig 2012: 1-7 - [c259]Marco D. Santambrogio, Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Christian Pilato, Georgi Gaydadjiev, Dirk Stroobandt, Tom Davidson, Tobias Becker, Tim Todman, Wayne Luk, Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Donatella Sciuto:
Smart technologies for effective reconfiguration: The FASTER approach. ReCoSoC 2012: 1-7 - 2011
- [j65]Kuen Hung Tsoi, Wayne Luk:
Power profiling and optimization for heterogeneous multi-core systems. SIGARCH Comput. Archit. News 39(4): 8-13 (2011) - [j64]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes:
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. Trans. High Perform. Embed. Archit. Compil. 4: 63-83 (2011) - [j63]William George Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer:
Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation. Trans. High Perform. Embed. Archit. Compil. 4: 354-369 (2011) - [j62]Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk:
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. 58(8): 3701-3716 (2011) - [j61]Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert:
Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1048-1061 (2011) - [j60]Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
An Analytical Model Relating FPGA Architecture to Logic Density and Depth. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2229-2242 (2011) - [c258]Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk:
FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design. ARC 2011: 181-192 - [c257]Stewart Denholm, Kuen Hung Tsoi, Peter R. Pietzuch, Wayne Luk:
CusComNet: A customisable network for reconfigurable heterogeneous clusters. ASAP 2011: 9-16 - [c256]Gary Chun Tak Chow, K. W. Kwok, Wayne Luk, Philip Heng Wai Leong:
Mixed Precision Processing in Reconfigurable Systems. FCCM 2011: 17-24 - [c255]Qiwei Jin, Wayne Luk, David B. Thomas:
On Comparing Financial Option Price Solvers on FPGA. FCCM 2011: 89-92 - [c254]Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk:
A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only). FPGA 2011: 281 - [c253]Qiwei Jin, Wayne Luk, David B. Thomas:
Unifying Finite Difference Option-Pricing for Hardware Acceleration. FPL 2011: 6-9 - [c252]Xinyu Niu, Kuen Hung Tsoi, Wayne Luk:
Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking. FPL 2011: 545-550 - [c251]Brahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj:
A framework for FPGA acceleration of large graph problems: Graphlet counting case study. FPT 2011: 1-8 - [c250]Qiang Liu, Wayne Luk:
Objective-driven workload allocation in heterogeneous computing systems. FPT 2011: 1-4 - [c249]Adrien Le Masle, Gary Chun Tak Chow, Wayne Luk:
Constant power reconfigurable computing. FPT 2011: 1-8 - [c248]Kong Woei Susanto, Wayne Luk:
Automating formal verification of customized soft-processors. FPT 2011: 1-8 - [c247]Chi Wai Yu, Fred Cox, Wayne Luk, Ray C. C. Cheung:
Hydrate: Hybrid Reconfigurable Architecture Expressions. FPT 2011: 1-4 - [c246]Andreas Kirkeby Fidjeland, Wayne Luk, Stephen H. Muggleton:
Customisable Multi-Processor Acceleration of Inductive Logic Programming. ILP (Late Breaking Papers) 2011: 123-141 - [c245]Tobias Becker, Qiwei Jin, Wayne Luk, Stephen Weston:
Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing. ReConFig 2011: 176-181 - [c244]Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev:
Power adaptive computing system design in energy harvesting environment. ICSAMOS 2011: 33-40 - [c243]Adrien Le Masle, Wayne Luk, Csaba Andras Moritz:
Parametrized hardware architectures for the Lucas primality test. ICSAMOS 2011: 124-131 - 2010
- [j59]Yuet Ming Lam, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk:
Multiloop Parallelisation Using Unrolling and Fission. Int. J. Reconfigurable Comput. 2010: 475620:1-475620:10 (2010) - [j58]Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfigurable Comput. 2010: 787405:1-787405:9 (2010) - [j57]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. 43(2): 188-201 (2010) - [j56]Koen Bertels, Vlad Mihai Sima, Yana Yankova, Georgi Kuzmanov, Wayne Luk, José Gabriel F. Coutinho, Fabrizio Ferrandi, Christian Pilato, Marco Lattuada, Donatella Sciuto, Andrea Michelotti:
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms. IEEE Micro 30(5): 88-97 (2010) - [j55]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk:
Efficient reconfigurable design for pricing asian options. SIGARCH Comput. Archit. News 38(4): 14-20 (2010) - [j54]Kuen Hung Tsoi, Anson H. T. Tse, Peter R. Pietzuch, Wayne Luk:
Programming framework for clusters with heterogeneous accelerators. SIGARCH Comput. Archit. News 38(4): 53-59 (2010) - [j53]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes:
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. IEEE Trans. Computers 59(4): 433-448 (2010) - [j52]Haohuan Fu, Oskar Mencer, Wayne Luk:
FPGA Designs with Optimized Logarithmic Arithmetic. IEEE Trans. Computers 59(7): 1000-1006 (2010) - [j51]Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen:
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. 15(2): 14:1-14:24 (2010) - [c242]Adrien Le Masle, Wayne Luk, Jared Eldredge, Kristopher Carver:
Parametric Encryption Hardware Design. ARC 2010: 68-79 - [c241]Adrien Le Masle, Wayne Luk:
Design space exploration of parametric pipelined designs. ASAP 2010: 47-54 - [c240]David B. Thomas, Wayne Luk:
An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers. ASAP 2010: 208-215 - [c239]Stephen Wray, Wayne Luk, Peter R. Pietzuch:
Exploring algorithmic trading in reconfigurable hardware. ASAP 2010: 325-328 - [c238]Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung:
Exploration of hardware sharing for image encoders. DATE 2010: 1737-1742 - [c237]Qiang Liu, Tim Todman, Wayne Luk:
Combining optimizations in automated low power design. DATE 2010: 1791-1796 - [c236]Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides:
Customizable Composition and Parameterization of Hardware Design Transformations. DSD 2010: 595-602 - [c235]Tobias Becker, Wayne Luk, Peter Y. K. Cheung:
Energy-Aware Optimisation for Run-Time Reconfiguration. FCCM 2010: 55-62 - [c234]Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides:
A Scripting Engine for Combining Design Transformations. FCCM 2010: 255-258 - [c233]Kuen Hung Tsoi, Wayne Luk:
Axel: a heterogeneous cluster with FPGAs and GPUs. FPGA 2010: 115-124 - [c232]David B. Thomas, Wayne Luk:
FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers. FPL 2010: 77-82 - [c231]Stephen Wray, Wayne Luk, Peter R. Pietzuch:
Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine. FPL 2010: 163-166 - [c230]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk:
Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. FPL 2010: 364-367 - [c229]Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Heng Wai Leong:
A Karatsuba-Based Montgomery Multiplier. FPL 2010: 434-437 - [c228]Brahim Betkaoui, David B. Thomas, Wayne Luk:
Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. FPT 2010: 94-101 - [c227]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk:
Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. FPT 2010: 233-240 - [c226]Vinay Sriram, David D. Cox, Kuen Hung Tsoi, Wayne Luk:
Towards an embedded biologically-inspired machine vision processor. FPT 2010: 273-278 - [c225]Qiang Liu, Tim Todman, Kuen Hung Tsoi, Wayne Luk:
Convex models for accelerating applications on FPGA-based clusters. FPT 2010: 495-498 - [c224]Tobias Becker, Markus Koester, Wayne Luk:
Automated placement of reconfigurable regions for relocatable modules. ISCAS 2010: 3341-3344
2000 – 2009
- 2009
- [j50]Haohuan Fu, William George Osborne, Robert G. Clapp, Oskar Mencer, Wayne Luk:
Accelerating Seismic Computations Using Customized Number Representations on FPGAs. EURASIP J. Embed. Syst. 2009 (2009) - [j49]Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk:
High-throughput one-dimensional median and weighted median filters on FPGA. IET Comput. Digit. Tech. 3(4): 384-394 (2009) - [j48]Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope:
Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models. ACM Trans. Reconfigurable Technol. Syst. 2(4): 21:1-21:17 (2009) - [j47]Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor:
Hierarchical Segmentation for Hardware Function Evaluation. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 103-116 (2009) - [j46]Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Floating-Point FPGA: Architecture and Modeling. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1709-1718 (2009) - [c223]Tobias Becker, Wayne Luk, Peter Y. K. Cheung:
Parametric Design for Reconfigurable Software-Defined Radio. ARC 2009: 15-26 - [c222]Julien Lamoureux, Tony Field, Wayne Luk:
Accelerating a Virtual Ecology Model with FPGAs. ASAP 2009: 67-74 - [c221]Andreas Fidjeland, Etienne B. Roesch, Murray Shanahan, Wayne Luk:
NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs. ASAP 2009: 137-144 - [c220]Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128 - [c219]Philip G. Potter, Wayne Luk, Peter Y. K. Cheung:
Partition-based exploration for reconfigurable JPEG designs. DATE 2009: 886-889 - [c218]Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann:
Design optimizations to improve placeability of partial reconfiguration modules. DATE 2009: 976-981 - [c217]Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson:
Harnessing Human Computation Cycles for the FPGA Placement Problem. ERSA 2009: 188-194 - [c216]Anson H. T. Tse, David B. Thomas, Wayne Luk:
Accelerating Quadrature Methods for Option Valuation. FCCM 2009: 29-36 - [c215]David B. Thomas, Wayne Luk:
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. FCCM 2009: 45-52 - [c214]Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen:
Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM 2009: 131-138 - [c213]David B. Thomas, Lee W. Howes, Wayne Luk:
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. FPGA 2009: 63-72 - [c212]Qiwei Jin, David B. Thomas, Wayne Luk:
Exploring reconfigurable architectures for explicit finite difference option pricing models. FPL 2009: 73-78 - [c211]Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
Modeling post-techmapping and post-clustering FPGA circuit depth. FPL 2009: 205-211 - [c210]Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides:
Optimising designs by combining model-based and pattern-based transformations. FPL 2009: 308-313 - [c209]Gareth W. Morris, David B. Thomas, Wayne Luk:
FPGA Accelerated Low-Latency Market Data Feed Processing. Hot Interconnects 2009: 83-89 - [c208]Wayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William George Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong:
A high-level compilation toolchain for heterogeneous systems. SoCC 2009: 9-18 - [c207]Chun Hok Ho, Wayne Luk, Jakub Szefer, Ruby B. Lee:
Tuning instruction customisation for reconfigurable system-on-chip. SoCC 2009: 61-64 - [c206]Kong Woei Susanto, Tim Todman, José Gabriel F. Coutinho, Wayne Luk:
Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation. SOFSEM 2009: 509-520 - 2008
- [j45]Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfigurable Comput. 2008: 736203:1-736203:10 (2008) - [j44]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
Custom parallel caching schemes for hardware-accelerated image compression. J. Real Time Image Process. 3(4): 289-302 (2008) - [j43]Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor:
Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations. IEEE Trans. Computers 57(5): 686-701 (2008) - [j42]Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk:
CHIPS: Custom Hardware Instruction Processor Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 528-541 (2008) - [j41]Duncan A. Buell, Wayne Luk:
Introduction. ACM Trans. Reconfigurable Technol. Syst. 1(1): 1:1-1:2 (2008) - [j40]Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk:
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. ACM Trans. Reconfigurable Technol. Syst. 1(1): 7:1-7:25 (2008) - [j39]David B. Thomas, Wayne Luk:
Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware. ACM Trans. Reconfigurable Technol. Syst. 1(2): 12:1-12:29 (2008) - [j38]Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker Dulay, Emil C. Lupu, Geoffrey Brown:
Reconfigurable Architecture for Network Flow Analysis. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 57-65 (2008) - [j37]Wayne Luk, Yvon Savaria, Oskar Mencer:
Guest Editorial: 20 Years of ASAP. J. Signal Process. Syst. 53(1-2): 1-2 (2008) - [c205]Julien Lamoureux, Wayne Luk:
An Overview of Low-Power Techniques for Field-Programmable Gate Arrays. AHS 2008: 338-345 - [c204]Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk:
An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC 2008: 219-230 - [c203]Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope:
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. ARC 2008: 243-253 - [c202]Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar:
Fast custom instruction identification by convex subgraph enumeration. ASAP 2008: 1-6 - [c201]David B. Thomas, Wayne Luk:
Resource efficient generators for the floating-point uniform and exponential distributions. ASAP 2008: 102-107 - [c200]Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao Lu, Xiaoxiang Shi, Wayne Luk:
Reconfigurable acceleration of microphone array algorithms for speech enhancement. ASAP 2008: 203-208 - [c199]Andreas Fidjeland, Wayne Luk, Stephen H. Muggleton:
A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming. BCS Int. Acad. Conf. 2008: 318-330 - [c198]Ben Cope, Peter Y. K. Cheung, Wayne Luk:
Using Reconfigurable Logic to Optimise GPU Memory Accesses. DATE 2008: 44-49 - [c197]William George Osborne, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer:
Power-Aware and Branch-Aware Word-Length Optimization. FCCM 2008: 129-138 - [c196]David B. Thomas, Wayne Luk:
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. FCCM 2008: 229-238 - [c195]David B. Thomas, Wayne Luk:
FPGA-optimised high-quality uniform random number generators. FPGA 2008: 235-244 - [c194]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258 - [c193]Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
An analytical model describing the relationships between logic architecture and FPGA density. FPL 2008: 221-226 - [c192]Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Rapid estimation of power consumption for hybrid FPGAs. FPL 2008: 227-232 - [c191]David B. Thomas, Wayne Luk:
Sampling from the exponential distribution using independent Bernoulli variates. FPL 2008: 239-244 - [c190]Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong:
Mapping and scheduling with task clustering for heterogeneous computing systems. FPL 2008: 275-280 - [c189]Markus Koester, Wayne Luk, Geoffrey Brown:
A hardware compilation flow for instance-specific VLIW cores. FPL 2008: 619-622 - [c188]Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694 - [c187]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined signaling for on-FPGA communication. FPT 2008: 9-16 - [c186]Haohuan Fu, Oskar Mencer, Wayne Luk:
Optimizing residue arithmetic on FPGAs. FPT 2008: 41-48 - [c185]Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton:
Optimizing coarse-grained units in floating point hybrid FPGA. FPT 2008: 57-64 - [c184]David B. Thomas, Wayne Luk:
Estimation of sample mean and variance for Monte-Carlo simulations. FPT 2008: 89-96 - [c183]Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong:
Unrolling-based loop mapping and scheduling. FPT 2008: 321-324 - [c182]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214 - [c181]Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk:
Smart Enumeration: A Systematic Approach to Exhaustive Search. PATMOS 2008: 429-438 - [c180]Ben Cope, Peter Y. K. Cheung, Wayne Luk:
Systematic design space exploration for customisable multi-processor architectures. ICSAMOS 2008: 57-64 - [c179]William George Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer:
Reconfigurable design with clock gating. ICSAMOS 2008: 187-194 - [c178]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10 - [c177]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58 - 2007
- [j36]David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor:
Gaussian random number generators. ACM Comput. Surv. 39(4): 11 (2007) - [j35]David B. Thomas, Wayne Luk:
Non-uniform random number generation through piecewise linear approximations. IET Comput. Digit. Tech. 1(4): 312-321 (2007) - [j34]Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk:
Real-time hardware acceleration of the trace transform. J. Real Time Image Process. 2(4): 235-248 (2007) - [j33]Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam:
High-Performance Embedded Architecture and Compilation Roadmap. Trans. High Perform. Embed. Archit. Compil. 1: 5-29 (2007) - [j32]Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor:
Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 952-962 (2007) - [j31]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1003-1016 (2007) - [j30]José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, Benny Lo, Wayne Luk, Oskar Mencer, Guang-Zhong Yang:
Designing a Posture Analysis System with Hardware Implementation. J. VLSI Signal Process. 47(1): 33-45 (2007) - [j29]David B. Thomas, Wayne Luk:
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. J. VLSI Signal Process. 47(1): 77-92 (2007) - [c176]David B. Thomas, Wayne Luk, Michael Stumpf:
Reconfigurable Hardware Acceleration of Canonical Graph Labelling. ARC 2007: 302-313 - [c175]David B. Thomas, Jacob A. Bower, Wayne Luk:
Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. ASAP 2007: 168-173 - [c174]Ben Cope, Peter Y. K. Cheung, Wayne Luk:
Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. ASAP 2007: 308-313 - [c173]Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar:
Optimizing instruction-set extensible processors under data bandwidth constraints. DATE 2007: 588-593 - [c172]David B. Thomas, Wayne Luk:
Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. FCCM 2007: 3-12 - [c171]Tobias Becker, Wayne Luk, Peter Y. K. Cheung:
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. FCCM 2007: 35-44 - [c170]Haohuan Fu, Oskar Mencer, Wayne Luk:
Optimizing Logarithmic Arithmetic on FPGAs. FCCM 2007: 163-172 - [c169]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
A Hybrid Memory Sub-system for Video Coding Applications. FCCM 2007: 317-318 - [c168]Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton:
A synthesizable datapath-oriented embedded FPGA fabric. FPGA 2007: 33-41 - [c167]Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. FPL 2007: 196-201 - [c166]William George Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer:
Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. FPL 2007: 617-620 - [c165]William George Osborne, José Gabriel F. Coutinho, Ray C. C. Cheung, Wayne Luk, Oskar Mencer:
Instrumented Multi-Stage Word-Length Optimization. FPT 2007: 89-96 - [c164]David B. Thomas, Wayne Luk:
A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations. FPT 2007: 97-104 - [c163]Jacob A. Bower, Wei Ning Cho, Wayne Luk:
Unifying FPGA Hardware Development. FPT 2007: 113-120 - [c162]Kentaro Sano, Oliver Pell, Wayne Luk, Satoru Yamamoto:
FPGA-based Streaming Computation for Lattice Boltzmann Method. FPT 2007: 233-236 - [c161]Tim Todman, Haofan Fu, Oskar Mencer, Wayne Luk:
Improving Bounds for FPGA Logic Minimization. FPT 2007: 245-248 - [c160]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182 - [c159]Tim Todman, Wayne Luk:
Domain Specific Transformations for Hardware Ray Tracing. CPA 2007: 479-492 - [i1]Tero Rissa, Adam Donlin, Wayne Luk:
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. CoRR abs/0710.4845 (2007) - 2006
- [j28]Steve McKeever, Wayne Luk:
Provably-correct hardware compilation tools based on pass separation techniques. Formal Aspects Comput. 18(2): 120-142 (2006) - [j27]Jacob A. Bower, Wayne Luk, Oskar Mencer, Michael J. Flynn, Martin Morf:
Dynamic clock-frequencies for FPGAs. Microprocess. Microsystems 30(6): 388-397 (2006) - [j26]Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong:
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis. IEEE Trans. Computers 55(6): 659-671 (2006) - [j25]Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides:
Accuracy-Guaranteed Bit-Width Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1990-2000 (2006) - [c158]Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC 2006: 205-216 - [c157]Sherif Yusuf, Wayne Luk, M. K. N. Szeto, William George Osborne:
UNITE: Uniform Hardware-Based Network Intrusion deTection Engine. ARC 2006: 389-400 - [c156]Arran Derbyshire, Tobias Becker, Wayne Luk:
Incremental elaboration for run-time reconfigurable hardware designs. CASES 2006: 93-102 - [c155]Robert G. Dimond, Oskar Mencer, Wayne Luk:
Automating processor customisation: optimised memory access and resource sharing. DATE 2006: 206-211 - [c154]Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk:
Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation. ERSA 2006: 184-190 - [c153]Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo:
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM 2006: 35-44 - [c152]David B. Thomas, Wayne Luk:
Efficient Hardware Generation of Random Variates with Arbitrary Distributions. FCCM 2006: 57-66 - [c151]Robert G. Dimond, Oskar Mencer, Wayne Luk:
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA. FCCM 2006: 175-184 - [c150]Oliver Pell, Wayne Luk:
Generating Parametrised Hardware Libraries from Higher-Order Descriptions. FCCM 2006: 297-298 - [c149]Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk:
Efficient Realtime FPGA Implementation of the Trace Transform. FPL 2006: 1-6 - [c148]Andreas Fidjeland, Wayne Luk:
Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming. FPL 2006: 1-6 - [c147]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8 - [c146]Oliver Pell, Wayne Luk:
Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information. FPL 2006: 1-6 - [c145]David B. Thomas, Wayne Luk:
Non-Uniform Random Number Generation Through Piecewise Linear Approximations. FPL 2006: 1-6 - [c144]Dong-U Lee, Ray C. C. Cheung, John D. Villasenor, Wayne Luk:
Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation. FPT 2006: 33-40 - [c143]Samuel Bayliss, Christos-Savvas Bouganis, George A. Constantinides, Wayne Luk:
An FPGA implementation of the simplex algorithm. FPT 2006: 49-56 - [c142]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT 2006: 333-336 - [c141]Haohuan Fu, Oskar Mencer, Wayne Luk:
Comparing floating-point and logarithmic number representations for reconfigurable acceleration. FPT 2006: 337-340 - [c140]David B. Thomas, Jacob A. Bower, Wayne Luk:
Hardware architectures for Monte-Carlo based financial simulations. FPT 2006: 377-380 - [c139]Wayne Luk, Kubilay Atasu, Robert G. Dimond, Oskar Mencer:
Towards optimal custom instruction processors. Hot Chips Symposium 2006: 1-23 - [c138]Jacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer:
A Reconfigurable Simulation Framework for Financial Computation. ReConFig 2006: 30-38 - [c137]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176 - 2005
- [j24]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
Hardware/software codesign: a systematic approach targeting data-intensive applications. IEEE Signal Process. Mag. 22(3): 14-22 (2005) - [j23]Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk:
Optimizing Hardware Function Evaluation. IEEE Trans. Computers 54(12): 1520-1531 (2005) - [j22]Tim Todman, José Gabriel F. Coutinho, Wayne Luk:
Customisable Hardware Compilation. J. Supercomput. 32(2): 119-137 (2005) - [j21]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 39-57 (2005) - [j20]Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong:
A hardware Gaussian noise generator using the Wallace method. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 911-920 (2005) - [j19]Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung:
Customizable elliptic curve cryptosystems. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1048-1059 (2005) - [c136]Andreas Fidjeland, Wayne Luk:
Customising Application-Speci.c Multiprocessor Systems: a Case Study. ASAP 2005: 239-246 - [c135]Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung:
Automating custom-precision function evaluation for embedded processors. CASES 2005: 22-31 - [c134]Oliver Pell, Wayne Luk:
Resolving Quartz Overloading. CHARME 2005: 380-383 - [c133]Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk:
MiniBit: bit-width optimization via affine arithmetic. DAC 2005: 837-840 - [c132]Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk:
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. DATE 2005: 8-13 - [c131]Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung:
Reconfigurable Elliptic Curve Cryptosystems on a Chip. DATE 2005: 24-29 - [c130]Wayne Luk, Sherif Yusuf, Morris Sloman, Geoffrey Brown, Emil C. Lupu, Naranker Dulay:
A Combined Hardware-Software Architecture for Network Flow. ERSA 2005: 149-155 - [c129]Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen:
Cell Based Motion Estimators for Reconfigurable Platforms. ERSA 2005: 218-224 - [c128]Paul Baker, Tim Todman, Henry Styles, Wayne Luk:
Reconfigurable Designs for Radiosity. FCCM 2005: 95-104 - [c127]José Gabriel F. Coutinho, Jun Jiang, Wayne Luk:
Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation. FCCM 2005: 245-254 - [c126]Robert G. Dimond, Oskar Mencer, Wayne Luk:
CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools. FPL 2005: 1-6 - [c125]Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk:
Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. FPL 2005: 142-147 - [c124]Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk:
Ziggurat-based Hardware Gaussian Random Number Generator. FPL 2005: 275-280 - [c123]Henry Styles, Wayne Luk:
Compilation and Management of Phase-Optimized Reconfigurable Systems. FPL 2005: 311-316 - [c122]Sherif Yusuf, Wayne Luk:
Bitwise Optimised CAM for Network Intrusion Detection Systems. FPL 2005: 444-449 - [c121]David B. Thomas, Wayne Luk:
High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences. FPT 2005: 61-68 - [c120]M. P. T. Juvonen, José Gabriel F. Coutinho, J. L. Wang, Benny Lo, Wayne Luk, Oskar Mencer, Guang-Zhong Yang:
Custom Hardware Architectures for Posture Analysis. FPT 2005: 77-84 - [c119]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt:
Have GPUs Made FPGAs Redundant in the Field of Video Processing? FPT 2005: 111-118 - [c118]Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton:
Dynamic Voltage Scaling for Commercial FPGAs. FPT 2005: 173-180 - [c117]Guanglie Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, Chris C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk:
Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. FPT 2005: 215-222 - [c116]Andreas Fidjeland, Wayne Luk:
An Overview of High-Level Synthesis of Multiprocessors for Logic Programming. FPT 2005: 333-334 - [c115]Oliver Pell, Wayne Luk:
Quartz: a framework for correct and efficient reconfigurable design. ReConFig 2005 - [c114]David B. Thomas, Wayne Luk:
High quality uniform random number generation for massively parallel simulations in FPGA. ReConFig 2005 - 2004
- [b1]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthesis and optimization of DSP algorithms. Kluwer 2004, ISBN 978-1-4020-7930-6, pp. I-XI, 1-164 - [j18]Henry Styles, Wayne Luk:
Exploiting Program Branch Probabilities in Hardware Compilation. IEEE Trans. Computers 53(11): 1408-1419 (2004) - [j17]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
A Gaussian Noise Generator for Hardware-Based Simulations. IEEE Trans. Computers 53(12): 1523-1534 (2004) - [j16]Oskar Mencer, Wayne Luk:
Parameterized High Throughput Function Evaluation for FPGAs. J. VLSI Signal Process. 36(1): 17-25 (2004) - [c113]W. W. S. Chu, Robert G. Dimond, S. Perrott, S. P. Seng, Wayne Luk:
Customisable EPIC Processor: Architecture and Tools. DATE 2004: 236-241 - [c112]Tero Rissa, Adam Donlin, Wayne Luk:
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. DATE 2004: 253-258 - [c111]Tim Todman, José Gabriel F. Coutinho, Wayne Luk:
Customisable Hardware Compilation. ERSA 2004: 18-28 - [c110]Tero Rissa, Wayne Luk, Peter Y. K. Cheung:
Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. ERSA 2004: 184-193 - [c109]Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung:
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. FCCM 2004: 79-88 - [c108]Dong-U Lee, Wayne Luk, Connie Wang, Christopher R. Jones, Michael Smith, John D. Villasenor:
A Flexible Hardware Encoder for Low-Density Parity-Check Codes. FCCM 2004: 101-111 - [c107]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272 - [c106]Tero Rissa, Peter Y. K. Cheung, Wayne Luk:
SoftSONIC: A Customisable Modular Platform for Video Applications. FPL 2004: 54-63 - [c105]Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk:
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. FPL 2004: 364-373 - [c104]Tim Todman, Wayne Luk:
Methods and Tools for High-Resolution Imaging. FPL 2004: 627-636 - [c103]Steven J. E. Wilton, Su-Shin Ang, Wayne Luk:
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. FPL 2004: 719-728 - [c102]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051 - [c101]David B. Thomas, Wayne Luk:
Implementing Graphics Shaders Using FPGAs. FPL 2004: 1173 - [c100]Tim Todman, Wayne Luk:
Memory optimisations for high-resolution imaging. FPT 2004: 153-160 - [c99]Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk:
Adaptive range reduction for hardware function evaluation. FPT 2004: 169-176 - [c98]Ray C. C. Cheung, Ashley Brown, Wayne Luk, Peter Y. K. Cheung:
A scalable hardware architecture for prime number validation. FPT 2004: 177-184 - [c97]Henry Styles, David B. Thomas, Wayne Luk:
Pipelining designs with loop-carried dependencies. FPT 2004: 255-262 - [c96]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Scalable structured data access by combining autonomous memory blocks. FPT 2004: 457-460 - [c95]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Autonomous Memory Block for reconfigurable computing. ISCAS (2) 2004: 581-584 - [c94]Tero Rissa, Wayne Luk:
Reduction of design complexity using virtual hardware platforms. SoC 2004 - [c93]Wayne Luk:
Customising Processors: Design-Time and Run-Time Opportunities. SAMOS 2004: 49-58 - [c92]Nicolas Telle, Wayne Luk, Ray C. C. Cheung:
Customising Hardware Designs for Elliptic Curve Cryptography. SAMOS 2004: 274-283 - 2003
- [j15]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Wordlength optimization for linear digital signal processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1432-1442 (2003) - [j14]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 334-354 (2003) - [c91]Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai:
PyHDL: Hardware Scripting with Python. Engineering of Reconfigurable Systems and Algorithms 2003: 288-291 - [c90]T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay:
Compiling Policy Descriptions into Reconfigurable Firewall Processors. FCCM 2003: 39- - [c89]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
A Hardware Gaussian Noise Generator for Channel Code Evaluation. FCCM 2003: 69- - [c88]Tim Todman, Wayne Luk:
Real-time Extensions to a C-like Hardware Description Language. FCCM 2003: 302-304 - [c87]Henry Styles, Wayne Luk:
Branch Optimisation Techniques for Hardware Compilation. FPL 2003: 324-333 - [c86]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. FPL 2003: 396-405 - [c85]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615 - [c84]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
Non-uniform Segmentation for Hardware Function Evaluation. FPL 2003: 796-807 - [c83]T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay:
Irregular Reconfigurable CAM Structures for Firewall Applications. FPL 2003: 890-899 - [c82]Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai:
Hardware Design with a Scripting Language. FPL 2003: 1040-1043 - [c81]Jun Jiang, Wayne Luk, Daniel Rueckert:
FPGA-Based Computation of Free-Form Deformations. FPL 2003: 1057-1061 - [c80]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. FPL 2003: 1071-1074 - [c79]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
Hierarchical segmentation schemes for function evaluation. FPT 2003: 92-99 - [c78]T. K. Lee, Arran Derbyshire, Wayne Luk, Peter Y. K. Cheung:
High-level language extensions for run-time reconfigurable systems. FPT 2003: 144-151 - [c77]Andreas Fidjeland, Wayne Luk:
Customising parallelism and caching for machine learning. FPT 2003: 204-211 - [c76]Jun Jiang, Wayne Luk, Daniel Rueckert:
FPGA-based computation of free-form deformations in medical image registration. FPT 2003: 234-241 - [c75]Oskar Mencer, David J. Pearce, Lee W. Howes, Wayne Luk:
Design space exploration with A Stream Compiler. FPT 2003: 270-277 - [c74]José Gabriel F. Coutinho, Wayne Luk:
Source-directed transformations for hardware compilation. FPT 2003: 278-285 - [c73]Steve McKeever, Wayne Luk, Arran Derbyshire:
Towards Verifying Parametrised Hardware Libraries with Relative Placement Information. HICSS 2003: 279 - [c72]Tim Todman, Wayne Luk:
Combining Imperative and Declarative Hardware Descriptions. HICSS 2003: 280 - [c71]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
Multitasking in hardware-software codesign for reconfigurable computer. ISCAS (5) 2003: 621-624 - 2002
- [j13]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. Des. Autom. Embed. Syst. 6(4): 425-449 (2002) - [c70]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. FCCM 2002: 3-12 - [c69]Jörn Gause, Peter Y. K. Cheung, Wayne Luk:
Reconfigurable Shape-Adaptive Template Matching Architectures. FCCM 2002: 98- - [c68]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Optimum Wordlength Allocation. FCCM 2002: 219-228 - [c67]Henry Styles, Wayne Luk:
Accelerating Radiosity Calculations Using Reconfigurable Platforms. FCCM 2002: 279-281 - [c66]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. FCCM 2002: 297-298 - [c65]Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi:
Customising Floating-Point Designs. FCCM 2002: 315-317 - [c64]Steve McKeever, Wayne Luk, Arran Derbyshire:
Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries. FMCAD 2002: 342-359 - [c63]Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang:
Automating Customisation of Floating-Point Designs. FPL 2002: 523-533 - [c62]Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung:
Run-Time Adaptive Flexible Instruction Processors. FPL 2002: 545-555 - [c61]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. FPL 2002: 1148-1151 - [c60]Arran Derbyshire, Wayne Luk:
Compiling run-time parametrisable designs. FPT 2002: 44-51 - [c59]José Gabriel F. Coutinho, Wayne Luk:
Optimising and adapting high-level hardware designs. FPT 2002: 150-157 - [c58]Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi:
Floating-point bitwidth analysis via automatic differentiation. FPT 2002: 158-165 - [c57]Andreas Fidjeland, Wayne Luk, Stephen H. Muggleton:
Scalable acceleration of inductive logic programs. FPT 2002: 252-259 - [c56]T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay:
Development framework for firewall processors. FPT 2002: 352-355 - [c55]Jun Jiang, Wayne Luk, Daniel Rueckert:
FPGA-based computation of free-form deformations. FPT 2002: 407-410 - [c54]Dong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung:
Incremental programming for reconfigurable engines. FPT 2002: 411-415 - [c53]Shay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong, Wayne Luk, Peter Y. K. Cheung:
PD-XML: extensible markup language for processor description. FPT 2002: 437-440 - [c52]Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen:
Strassen's matrix multiplication for customisable processors. FPT 2002: 453-456 - 2001
- [j12]Shaori Guo, Wayne Luk:
An integrated system for developing regular array designs. J. Syst. Archit. 47(3-4): 315-337 (2001) - [j11]Markus Weinhardt, Wayne Luk:
Pipeline vectorization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 234-248 (2001) - [j10]Nabeel Shirazi, Dan Benyamin, Wayne Luk, Peter Y. K. Cheung, Shaori Guo:
Quantitative Analysis of FPGA-based Database Searching. J. VLSI Signal Process. 28(1-2): 85-96 (2001) - [c51]Steve McKeever, Wayne Luk:
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques. CHARME 2001: 212-227 - [c50]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Heuristic datapath allocation for multiple wordlength systems. DATE 2001: 791-797 - [c49]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
The Multiple Wordlength Paradigm. FCCM 2001: 51-60 - [c48]Jörn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk:
The Effect of FPGA Granularity on Video Codec Implementations. FCCM 2001: 287-288 - [c47]Tim Todman, Wayne Luk:
Reconfigurable Designs for Ray Tracing. FCCM 2001: 300-301 - [c46]Nicolas Boullis, Oskar Mencer, Wayne Luk, Henry Styles:
Pipelined Function Evaluation on FPGAs. FCCM 2001: 304-306 - [c45]Markus Weinhardt, Wayne Luk:
Task-Parallel Programming of Reconfigurable Systems. FPL 2001: 172-181 - [c44]Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles:
Parameterized Function Evaluation for FPGAs. FPL 2001: 544-554 - [c43]Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk:
A Digit-Serial Structure for Reconfigurable Multipliers. FPL 2001: 565-573 - [c42]Allan Jaenicke, Wayne Luk:
Parameterised floating-point arithmetic on FPGAs. ICASSP 2001: 897-900 - [c41]Steve McKeever, Wayne Luk:
A declarative framework for developing parametrised hardware libraries. ICECS 2001: 1635-1638 - 2000
- [j9]Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk:
Video Image Processing with the Sonic Architecture. Computer 33(4): 50-57 (2000) - [j8]Jeffrey Arnold, Wayne Luk, Ken Pocek:
Guest Editors' Introduction. J. VLSI Signal Process. 24(2-3): 127 (2000) - [c40]Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung:
Flexible instruction processors. CASES 2000: 193-200 - [c39]Henry Styles, Wayne Luk:
Customizing Graphics Applications: Techniques and Programming Interface. FCCM 2000: 77-90 - [c38]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Multiple Precision for Resource Minimization. FCCM 2000: 307-308 - [c37]Markus Weinhardt, Wayne Luk:
Evaluating Hardware Compilation Techniques. FCCM 2000: 333-334 - [c36]Arran Derbyshire, Wayne Luk:
Combining Serialization and Reconfiguration for Convolver Designs. FCCM 2000: 344-346 - [c35]Jörn Gause, Peter Y. K. Cheung, Wayne Luk:
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. FPL 2000: 96-105 - [c34]Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk:
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. FPL 2000: 361-370 - [c33]Arran Derbyshire, Wayne Luk:
Combining Serialisation and Reconfiguration for FPGA Designs. FPL 2000: 636-645 - [c32]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Multiple-Wordlength Resource Binding. FPL 2000: 646-655 - [c31]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Roundoff-noise shaping in filter design. ISCAS 2000: 57-60
1990 – 1999
- 1999
- [c30]Markus Weinhardt, Wayne Luk:
Pipeline Vectorization for Reconfigurable Systems. FCCM 1999: 52-62 - [c29]Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung:
Reconfigurable Computing for Augmented Reality. FCCM 1999: 136-145 - [c28]Dan Benyamin, John D. Villasenor, Wayne Luk:
Optimizing FPGA-Based Vector Product Designs. FCCM 1999: 188- - [c27]Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone:
SONIC - A Plug-In Architecture for Video Processing. FCCM 1999: 280-281 - [c26]Florent de Dinechin, Wayne Luk, Steve McKeever:
Towards Adaptable Hierarchical Placement for FPGAs. FPGA 1999: 254 - [c25]Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone:
SONIC - A Plug-In Architecture for Video Processing. FPL 1999: 21-30 - [c24]Markus Weinhardt, Wayne Luk:
Memory Access Optimization and RAM Inference for Pipeline Vectorization. FPL 1999: 61-70 - [c23]Wayne Luk, Arran Derbyshire, Shaori Guo, D. Siganos:
Serial Hardware Libraries for Reconfigurable Designs. FPL 1999: 185-194 - [c22]Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung:
Quantitative Analysis of Run-Time Reconfigurable Database Search. FPL 1999: 253-263 - [c21]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. FPL 1999: 323-332 - 1998
- [c20]Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung:
Automating Production of Run-Time Reconfigurable Designs. FCCM 1998: 147-156 - [c19]Wayne Luk, Steve McKeever:
Pebble: A Language for Parametrised and Reconfigurable Hardware Design. FPL 1998: 9-18 - [c18]Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung:
Run-Time Management of Dynamically Recongigurable Designs. FPL 1998: 59-68 - [c17]Wayne Luk, P. Andreou, Arran Derbyshire, Florent Dupont de Dinechin, J. Rice, Nabeel Shirazi, D. Siganos:
A Reconfigurable Engine for Real-Time Video Processing. FPL 1998: 169-178 - 1997
- [j7]John O'Leary, Geoffrey Brown, Wayne Luk:
Verified Compilation of Communicating Processes into Clocked Circuits. Formal Aspects Comput. 9(5-6): 537-559 (1997) - [c16]Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung:
Compilation tools for run-time reconfigurable designs. FCCM 1997: 56-65 - [c15]Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford:
Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. FPL 1997: 91-100 - [c14]Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung:
Pipeline morphing and virtual pipelines. FPL 1997: 111-120 - [c13]Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk:
A reconfigurable data-localised array for morphological algorithms. FPL 1997: 344-353 - [e2]Wayne Luk, Peter Y. K. Cheung, Manfred Glesner:
Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings. Lecture Notes in Computer Science 1304, Springer 1997, ISBN 3-540-63465-7 [contents] - 1996
- [j6]Geoffrey Brown, Wayne Luk, John O'Leary:
Retargeting a Hardware Compiler Using Protokol Converters. Formal Aspects Comput. 8(2): 209-237 (1996) - [j5]Wayne Luk, Duncan A. Buell:
Guest editors' introduction. J. VLSI Signal Process. 12(1): 5 (1996) - [j4]Matthew Aubury, Wayne Luk:
Binomial filters. J. VLSI Signal Process. 12(1): 35-50 (1996) - [c12]Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung:
Modelling and optimising run-time reconfigurable systems. FCCM 1996: 167-176 - [c11]Wayne Luk, Shaori Guo, Nabeel Shirazi, N. Zhuang:
A Framework for Developing Parameterised FPGA Libraries. FPL 1996: 24-33 - 1995
- [c10]Wayne Luk:
A declarative approach to incremental custom computing. FCCM 1995: 164-172 - [c9]Adrian Lawrence, Andrew Kay, Wayne Luk, Toshio Nomura, Ian Page:
Using Reconfigurable Hardware to Speed up Product Development and Performance. FPL 1995: 111-118 - [c8]Shaori Guo, Wayne Luk:
Compiling Ruby into FPGAs. FPL 1995: 188-197 - [e1]Will Moore, Wayne Luk:
Field-Programmable Logic and Applications, 5th International Workshop, FPL '95, Oxford, UK, August 29 - September 1, 1995, Proceedings. Lecture Notes in Computer Science 975, Springer 1995, ISBN 3-540-60294-1 [contents] - 1994
- [c7]Geoffrey Brown, Wayne Luk, John O'Leary:
Retargeting a hardware compiler proof using protocol converters. ASYNC 1994: 54-63 - [c6]Wayne Luk, Teddy Wu:
Towards a declarative framework for hardware-software codesign. CODES 1994: 181-188 - [c5]Mat Newman, Wayne Luk, Ian Page:
Constraint-based Hierarchical Placement of Parallel Programs. FPL 1994: 220-229 - [c4]Shaori Guo, Wayne Luk, Penelope Probert:
Developing Parallel Architectures for Range and Image Sensors. ICRA 1994: 2205-2210 - 1993
- [j3]Wayne W. C. Luk:
Systematic serialisation of array-based architectures. Integr. 14(3): 333-360 (1993) - [j2]Will Moore, Wayne Luk:
Introduction. J. VLSI Signal Process. 6(2): 99-100 (1993) - 1992
- [c3]Wayne W. C. Luk:
Transformation techniques for serial array design. ASAP 1992: 574-588 - 1991
- [c2]Wayne W. C. Luk:
Pipelining and transposing heterogeneous array circuits. ASAP 1991: 263-277 - 1990
- [j1]Wayne Luk, Geoffrey Brown:
A Systolic LRU Processor and Its Top-Down Development. Sci. Comput. Program. 15(2-3): 217-233 (1990) - [c1]Wayne Luk:
Analysing parametrised designs by non-standard interpretation. ASAP 1990: 133-144
Coauthor Index
[c459] [i16] [j121] [i10] [c401] [j94] [c343] [c329] [j82] [c311] [c296] [j72] [c268] [j64] [j62] [j58] [j57] [j53] [j51] [c238] [c235] [j49] [c223] [c220] [c219] [c214] [j44] [c198] [c194] [c188] [c187] [c182] [c180] [c178] [c177] [j34] [j31] [c174] [c171] [c169] [c160] [c158] [c149] [c147] [c142] [c137] [j24] [j21] [j19] [c135] [c132] [c131] [c129] [c125] [c119] [b1] [j17] [c110] [c109] [c107] [c106] [c102] [c98] [c96] [c95] [j15] [j14] [c89] [c86] [c85] [c84] [c80] [c79] [c78] [c71] [j13] [c70] [c69] [c68] [c66] [c65] [c63] [c62] [c61] [c58] [c54] [c53] [c52] [j10] [c50] [c49] [c48] [c43] [j9] [c40] [c38] [c35] [c32] [c31] [c29] [c27] [c25] [c22] [c21] [c20] [c18] [c16] [c15] [c14] [c13] [e2] [c12]
José Gabriel F. Coutinho
aka: José Gabriel de Figueiredo Coutinho
aka: José Gabriel de Figueiredo Coutinho
[c487] [c483] [i23] [c477] [c465] [j128] [j127] [j126] [c441] [c438] [c421] [c407] [c400] [c387] [j101] [c362] [j96] [c334] [c312] [j83] [c308] [c298] [c295] [c288] [c287] [c279] [c278] [c275] [j63] [j59] [j56] [c210] [c208] [c206] [c197] [c190] [c183] [c179] [j30] [c166] [c165] [j22] [c127] [c120] [c111] [c74] [c59]
Andreas Fidjeland
aka: Andreas Kirkeby Fidjeland
aka: Andreas Kirkeby Fidjeland
Georgi Gaydadjiev
aka: Georgi Nedeltchev Gaydadjiev
aka: Georgi Nedeltchev Gaydadjiev
Philip H. W. Leong
aka: Philip Heng Wai Leong
aka: Philip Heng Wai Leong
[j129] [j123] [c435] [c419] [c415] [c404] [j113] [c369] [c356] [c324] [j69] [j63] [j52] [j50] [j42] [j37] [c202] [c197] [c186] [c181] [c179] [j30] [c173] [c170] [c166] [c165] [c161] [j27] [j25] [c155] [c151] [c141] [c139] [c138] [j23] [c135] [c133] [c126] [c120] [j16] [c109] [c105] [c99] [c91] [c82] [c75] [c58] [c46] [c44]
[j142] [j140] [j137] [j135] [j134] [j132] [c475] [j130] [c458] [i19] [i15] [j122] [c439] [c433] [c432] [c427] [c425] [j121] [c423] [c422] [c409] [c406] [i10] [j116] [c401] [c398] [c397] [c395] [c394] [c392] [c391] [c384] [c383] [c382] [i6] [j111] [c381] [c380] [c379] [c378] [c375] [c368] [c365] [c358] [c357] [c355] [p2] [j97] [j94] [j92] [j91] [c352] [c348] [c346] [c339] [j88] [c316] [c312] [c311] [c308] [c305] [c301] [c298] [c295] [c290] [c280] [c270] [c261] [c252]
[j153] [j150] [c489] [i31] [j142] [j140] [c486] [c483] [c482] [i23] [i22] [j137] [j134] [j132] [c478] [c477] [c475] [c468] [c467] [c466] [c462] [i20] [j130] [c459] [c456] [c451] [i18] [i16] [i15] [j122] [c440] [c439] [c436] [c433] [c432] [c427] [c423] [c422] [c411] [c408] [c406] [c394] [c392] [c391] [c383]
[j147] [j146] [c464] [c448] [c428] [j105] [j98] [j95] [c349] [c341] [i4] [i3] [c330] [c323] [c319] [i2] [j80] [j78] [j76] [c292] [j68] [c285] [c284] [c282] [c274] [c272] [c271] [c255] [c253] [c251] [j55] [c240] [c232] [c230] [c228] [c227] [j48] [c216] [c215] [c213] [c212] [c209] [j39] [c204] [c203] [c201] [c196] [c195] [c191] [c184] [j36] [j35] [j29] [c176] [c175] [c172] [c164] [c152] [c145] [c140] [c138] [c121] [c114] [c101] [c97]
Tim Todman
aka: Timothy John Todman
aka: Timothy John Todman
[c487] [j136] [c464] [c446] [c438] [c428] [c388] [j107] [c378] [p3] [c361] [c355] [p2] [p1] [j97] [c351] [j90] [c322] [c297] [j70] [j66] [c281] [c280] [c277] [c269] [c265] [c259] [c237] [c236] [c234] [c225] [c210] [c208] [c206] [c181] [c161] [c159] [j22] [c128] [c111] [c104] [c100] [c88] [c72] [c47]
Anson H. T. Tse
aka: Anson Hong Tak Tse
aka: Anson Hong Tak Tse
Steve Wilton
aka: Steven J. E. Wilton
aka: Steven J. E. Wilton
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Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-22 21:15 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
